ISL24211_14 Datasheet, PDF (8/12 Pages) Intersil Corporation – Programmable VCOM Calibrator with EEPROM and Output Buffer

ISL24211
By finding the difference of Equation 13 and Equation 12, the total
span of V_COM can be found:
V_COMSPAN
=
A
V_D
D
⎛
⎜
⎝
--_R----₁-^R--+--²--_R-----₂--_{⎠⎟⎞}
⎛
⎝
1
–
2^----51^----6^{- ⎠⎞}
⎛
⎜
⎝
2^----0^---R-R^---1-_S^----_E^---_T^-_{⎠⎟⎞}
(EQ. 14)
Assuming that the I_DVROUT(MIN) = 0 instead of I_STEP, the
expression in Equation 14 simplifies to:
V_COMSPAN
=
⎛
⎜
⎝
R^-R----₁^{-1---+-⋅---R-}R^---2-₂^--_{⎠⎟⎞}
⎛
⎜
⎝
2^{----A0----VR---D-}_S^---DE----_T^-_{⎠⎟⎞}
=
⎛
⎜
⎝
R^-R----₁^{-1---+-⋅---R-}R^---2-₂^--_{⎠⎟⎞}
I_DV
RO
U
T⁽
M
A
X)
(EQ. 15)
Power Supply Sequence
The recommended power supply sequencing is shown in
Figure 7. When applying power, V_DD should be applied before or
at the same time as AV_DD. The minimum time for t_VS is 0µs.
When removing power, the sequence of V_DD and AV_DD is not
important.
Do not remove V_DD or AV_DD within 100ms of the start of the
EEPROM programming cycle. Removing power before the
EEPROM programming cycle is completed may result in
corrupted data in the EEPROM.
DVR_OUT Pin Leakage Current
When the voltage on the DVR_OUT pin is greater than 10V, an
additional leakage current flows into the pin in addition to the
I_SET current. Figure 6 shows the I_SET current and the DVR_OUT
pin current for DVR_OUT pin voltage up to 19V. In applications
where the voltage on the DVR_OUT pin will be greater than 10V,
the actual output voltage will be lower than the voltage
calculated by Equation 8. The graph in Figure 6 was measured
with R_SET = 4.99kΩ.
0.30
REGISTER = 255
0.25
OUT PIN CURRENT
0.20
SET PIN CURRENT
0.15
0.10
0.05
0.00
0 2 4 6 8 10 12 14 16 18 20
OUT PIN VOLTAGE (V)
FIGURE 6. DVR_OUT PIN LEAKAGE CURRENT
V_DD
A_VDD
t_VS
FIGURE 7. POWER SUPPLY SEQUENCE
Operating and Programming
Supply Voltage and Current
To program the EEPROM, AV_DD must be ≥10.8V. If programming
is not required, the ISL24211 will operate over an AV_DD range of
4.5V to 19V.
During EEPROM programming, I_DD and I_AVDD will temporarily be
higher than their quiescent currents. Figure 8 shows a typical I_DD
and I_AVDD current profile during EEPROM programming. The
current pulses are Erase and Write cycles. The EEPROM
programming algorithm is shown in Figure 9. The algorithm
attempts up to 4 erase cycles and 4 programming cycles,
however typical parts only require 1 cycle of each, sometimes 2
when AV_DD is near the minimum 10.8V limit.
2.7mA
200µA
50µA
90µA
IP
~1ms
25µA
100ms
Max
FIGURE 8. I_DD AND I_AVDD CURRENT PROFILE DURING EEPROM
PROGRAMMING
8
FN7585.0
February 23, 2011