ISL24211_14 Datasheet, PDF (5/12 Pages) Intersil Corporation – Programmable VCOM Calibrator with EEPROM and Output Buffer

ISL24211
Electrical Specifications Test Conditions: V_DD = 3.3V, AV_DD = 18V, R_SET = 5kΩ, R₁ = 10kΩ, R₂ = 10kΩ, (See Figure 5), V_{COM_OUT} pin
connected to IN_N, unless otherwise specified. Typicals are at T_A = +25°C. Boldface limits apply over the operating temperature range,
-40°C to +85°C. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 6)
MAX
TYP (Note 6) UNITS
V_OH Output Swing High
I_SC
Short Circuit Current (Sinking)
Short Circuit Current (Sourcing)
SR Slew Rate (Rising)
I_L = 5mA
1kΩ || 8pF Load
17.85
17.9
300
430
450
555
70
116
V
mA
mA
V/µs
Slew Rate (Falling)
1kΩ || 8pF Load
50
93
V/µs
t_S
Settling Time to 0.2%
BW -3dB Bandwidth
I²C INPUTS AND OUTPUT
150
ns
60
MHz
V_{IH_I2C} SDA, SCL Logic 1 Input Voltage
1.44
V
V_{IL_I2C} SDA, SCL Logic 0 Input Voltage
0.55
V
V_{HYS_I2C} SDA, SCL Hysteresis
260
mV
I_{L_I2C} SDA, SCL Input Leakage Current
±1
µA
V_{OL_I2C} SDA Output Logic Low
I = -3mA
0.4
V
V_{IH_WP} WP Input Logic High
0.7V_DD
V
V_{IL_WP} WP Input Logic Low
0.3V_DD
V
V_{HYS_WP} WP Input Hysteresis
260
mV
I_{L_WP} WP Input Leakage Current
I²C TIMING
-0.20
-0.5
-1
µA
f_CLK
t_SCH
t_SCL
t_DSP
t_SDS
t_SDH
t_BUF
t_STS
t_STH
t_SPS
I²C Clock Frequency
I²C Clock High Time
I²C Clock Low Time
I²C Spike Rejection Filter Pulse Width
I²C Data Set Up Time
I²C Data Hold Time
I²C Time Between Stop and Start
I²C Repeated Start Condition Set-up
I²C Repeated Start Condition Hold
I²C Stop Condition Set-up
400
kHz
0.6
µs
1.3
µs
0
50
ns
250
ns
250
ns
200
µs
0.6
µs
0.6
µs
0.6
µs
C_SDA SDA Pin Capacitance
10
pF
C_SCL SCL Pin Capacitance
10
pF
t_WR EEPROM Write Cycle Time
100
ms
NOTE:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
5
FN7585.0
February 23, 2011