ISL23325 Datasheet, PDF (8/20 Pages) Intersil Corporation – Dual, 256-Tap, Low Voltage Digitally Controlled Potentiometer (XDCP™)

ISL23325
Serial Interface Specification For SCL, SDA, A0, A1, A2 unless otherwise noted. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 20)
TYP
(Note 8)
MAX
(Note 20)
UNITS
t_HD:DAT Input Data Hold Time
From SCL falling edge crossing
0
ns
70% of V_LOGIC to SDA entering
the 30% to 70% of V_LOGIC
window
t_SU:STO
t_HD:STO
t_DH
t_R
t_F
Cb
STOP Condition Set-up Time
From SCL rising edge crossing
600
70% of V_LOGIC, to SDA rising
edge crossing 30% of V_LOGIC
STOP Condition Hold Time for Read From SDA rising edge to SCL
or Write
falling edge; both crossing
70% of V_LOGIC
1300
Output Data Hold Time
From SCL falling edge crossing
0
30% of V_LOGIC, until SDA
enters the 30% to 70% of
V_LOGIC window.
I_OL = 3mA, V_LOGIC > 2V.
I_OL = 0.5mA, V_LOGIC < 2V
SDA and SCL Rise Time
From 30% to 70% of V_LOGIC 20 + 0.1 x Cb
SDA and SCL Fall Time
From 70% to 30% of V_LOGIC 20 + 0.1 x Cb
Capacitive Loading of SDA or SCL Total on-chip and off-chip
10
ns
ns
ns
250
ns
250
ns
400
pF
t_SU:A
A2, A1, A0 Setup Time
Before START condition
600
ns
t_HD:A
A2, A1, A0 Hold Time
After STOP condition
600
ns
NOTES:
8. Typical values are for T_A = +25°C and 3.3V supply voltages.
9. LSB = [V(RW)₂₅₅ – V(RW)₀]/255. V(RW)₂₅₅ and V(RW)₀ are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the incremental
voltage when changing from one tap to an adjacent tap.
10. ZS error = V(RW)₀/LSB.
11. FS error = [V(RW)₂₅₅ – V_CC]/LSB.
12. DNL = [V(RW)_i – V(RW)_i-1]/LSB-1, for i = 1 to 255. i is the DCP register setting.
13. INL = [V(RW)_i – i • LSB – V(RW)₀]/LSB for i = 1 to 255
14.
TC_V
=
M_------a_----x_---(_--V_----(_--R_-----W_-----)_--i--)_{----–----}M_-----i_--n_----(_---V_---(_---R_----W_------)_--i--)
V ( R W_i ( + 25 °C ) )
×
------¹----⁰----⁶-------
+ 165 °C
For i = 16 to 255 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper voltage
and Min( ) is the minimum value of the wiper voltage over the temperature range.
15. MI = |RW₂₅₅ – RW₀|/255. MI is a minimum increment. RW₂₅₅ and RW₀ are the measured resistances for the DCP register set to FF hex and 00
hex respectively.
16. Roffset = RW₀/MI, when measuring between RW and RL.
Roffset = RW₂₅₅/MI, when measuring between RW and RH.
17. RDNL = (RW_i – RW_i-1)/MI -1, for i = 16 to 255.
18. RINL = [RW_i – (MI • i) – RW₀]/MI, for i = 16 to 255.
19.
TC_R
=
[_---M_-----a_----x_---(_--R_-----i_--)_{---–-----}M_-----i_--n_----(_--R_----i_--)_---]
R i ( + 25 °C )
×
------¹----⁰----⁶-------
+ 165 °C
for i = 16 to 255, T = -40°C to +125°C. Max( ) is the maximum value of the resistance and Min( ) is the
minimum value of the resistance over the temperature range.
20. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
21. It is preferable to ramp up both the V_LOGIC and the V_CC supplies at the same time. If this is not possible, it is recommended to ramp-up the V_LOGIC
first followed by the V_CC.
22. VMATCH = [V(RWx)i - V(RWy)i]/LSB, for i = 1 to 255, x = 0 to 1 and y = 0 to 1.
23. RMATCH = (RWi,x - RWi,y)/MI, for i = 1 to 255 , x = 0 to 1 and y = 0 to 1.
8
FN7870.0
June 21, 2011