ISL23325 Datasheet, PDF (7/20 Pages) Intersil Corporation – Dual, 256-Tap, Low Voltage Digitally Controlled Potentiometer (XDCP™)

ISL23325
Operating Specifications V_CC = 2.7V to 5.5V, V_LOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated.
Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 20)
TYP
(Note 8)
MAX
(Note 20)
UNITS
t_DCP Wiper Response Time
SCL rising edge of the acknowledge bit
0.4
µs
after data byte to wiper new position
(Changes from 10% to 90% FS)
1.5
µs
W, U, T options specified top to bottom
3.5
µs
tShdnRec DCP Recall Time from Shutdown Mode SCL rising edge of the acknowledge bit
1.5
µs
after ACR data byte to wiper recalled
position and RH connection
V_CC,V_LOGIC V_{CC ,}V_LOGIC Ramp Rate
Ramp
(Note 21)
Ramp monotonic at any level
0.01
50
V/ms
Serial Interface Specification For SCL, SDA, A0, A1, A2 unless otherwise noted.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 20)
V_IL
V_IH
Hysteresis
V_OL
C_pin
f_SCL
t_sp
Input LOW Voltage
Input HIGH Voltage
SDA and SCL Input Buffer
Hysteresis
SDA Output Buffer LOW Voltage
SDA, SCL Pin Capacitance
SCL Frequency
Pulse Width Suppression Time at
SDA and SCL Inputs
V_LOGIC > 2V
V_LOGIC < 2V
I_OL = 3mA, V_LOGIC > 2V
I_OL = 1.5mA, V_LOGIC < 2V
Any pulse narrower than the
max spec is suppressed
-0.3
0.7 x V_LOGIC
0.05 x V_LOGIC
0.1 x V_LOGIC
0
t_AA
SCL Falling Edge to SDA Output SCL falling edge crossing 30%
Data Valid
of V_LOGIC, until SDA exits the
30% to 70% of V_LOGIC window
t_BUF
Time the Bus Must be Free Before SDA crossing 70% of V_LOGIC
the Start of a New Transmission during a STOP condition, to
SDA crossing 70% of V_LOGIC
during the following START
condition
1300
t_LOW
Clock LOW Time
t_HIGH
Clock HIGH Time
t_SU:STA
START Condition Set-up Time
t_HD:STA START Condition Hold Time
t_SU:DAT Input Data Set-up Time
Measured at the 30% of
V_LOGIC crossing
Measured at the 70% of
V_LOGIC crossing
SCL rising edge to SDA falling
edge; both crossing 70% of
V_LOGIC
From SDA falling edge
crossing 30% of V_LOGIC to SCL
falling edge crossing 70% of
V_LOGIC
From SDA exiting the 30% to
70% of V_LOGIC window, to SCL
rising edge crossing 30% of
V_LOGIC
1300
600
600
600
100
TYP
(Note 8)
10
MAX
(Note 20)
0.3 x V_LOGIC
V_LOGIC + 0.3
0.4
0.2 x V_LOGIC
400
50
900
UNITS
V
V
V
V
V
V
pF
kHz
ns
ns
ns
ns
ns
ns
ns
ns
7
FN7870.0
June 21, 2011