ISL23325 Datasheet, PDF (2/20 Pages) Intersil Corporation – Dual, 256-Tap, Low Voltage Digitally Controlled Potentiometer (XDCP™)

ISL23325
Block Diagram
V_LOGIC
V_CC
RH0
RH1
SCL
SDA
A0
A1
A2
I/O
BLOCK
LEVEL
SHIFTER
POWER UP
INTERFACE,
CONTROL
AND
STATUS
LOGIC
WR0
VOLATILE
REGISTER
AND
WIPER
CONTROL
CIRCUITRY
WR1
VOLATILE
REGISTER
AND
WIPER
CONTROL
CIRCUITRY
GND
Pin Configurations
ISL23325
(14 LD TSSOP)
TOP VIEW
GND 1
V_LOGIC 2
SDA 3
SCL 4
A0 5
A1 6
A2 7
14 V_CC
13 RL0
12 RW0
11 RH0
10 RH1
9 RW1
8 RL1
ISL23325
(16 LD µTQFN)
TOP VIEW
SDA 1
SCL 2
A0 3
A1 4
12 RW0
11 RH0
10 RH1
9 RW1
RW0 RL0
RW1 RL1
Pin Descriptions
TSSOP
1
2
µTQFN
6, 15
16
3
1
4
2
5
3
6
4
7
5
8
8
9
9
10
10
11
11
12
12
13
13
14
14
7
SYMBOL
DESCRIPTION
GND
V_LOGIC
Ground pin
I²C bus/logic supply. Range 1.2V to
5.5V
SDA Logic Pin - Serial bus data
input/open drain output
SCL Logic Pin - Serial bus clock input
A0 Logic Pin - Hardwire slave address
pin for I²C serial bus.
Range: V_LOGIC or GND
A1 Logic Pin - Hardwire slave address
pin for I²C serial bus.
Range: V_LOGIC or GND
A2 Logic Pin - Hardwire slave address
pin for I²C serial bus.
Range: V_LOGIC or GND
RL1 DCP1 “low” terminal
RW1 DCP1 wiper terminal
RH1 DCP1 “high” terminal
RH0 DCP0 “high” terminal
RW0 DCP0 wiper terminal
RL0 DCP0 “low” terminal
V_CC Analog power supply.
Range 1.7V to 5.5V
NC Not Connected
2
FN7870.0
June 21, 2011