ISL23325 Datasheet, PDF (15/20 Pages) Intersil Corporation – Dual, 256-Tap, Low Voltage Digitally Controlled Potentiometer (XDCP™)

ISL23325
POWER-UP
MID SCALE = 80H
USER PROGRAMMED
AFTER SHDN
SHDN ACTIVATED ^{SHDN RELEASED}
WIPER RESTORE TO
THE ORIGINAL POSITION
SHDN MODE
0
TIME (s)
FIGURE 26. SHUTDOWN MODE WIPER RESPONSE
I²C Serial Interface
The ISL23325 supports an I²C bidirectional bus oriented
protocol. The protocol defines any device that sends data onto
the bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the device
being controlled is the slave. The master always initiates data
transfers and provides the clock for both transmit and receive
operations. Therefore, the ISL23325 operates as a slave device
in all applications.
All communication over the I²C interface is conducted by sending
the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line must change only during SCL LOW
periods. SDA state changes during SCL HIGH are reserved for
indicating START and STOP conditions (see Figure 27). On
power-up of the ISL23325, the SDA pin is in the input mode.
All I²C interface operations must begin with a START condition,
which is a HIGH-to-LOW transition of SDA while SCL is HIGH. The
ISL23325 continuously monitors the SDA and SCL lines for the
START condition and does not respond to any command until this
condition is met (see Figure 27). A START condition is ignored
during the power-up of the device.
All I²C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while SCL is
HIGH (see Figure 27). A STOP condition at the end of a read
operation or at the end of a write operation places the device in
its standby mode.
An ACK (Acknowledge) is a software convention used to indicate
a successful data transfer. The transmitting device, either master
or slave, releases the SDA bus after transmitting eight bits.
During the ninth clock cycle, the receiver pulls the SDA line LOW
to acknowledge the reception of the eight bits of data
(see Figure 28).
The ISL23325 responds with an ACK after recognition of a START
condition followed by a valid Identification Byte, and once again
after successful receipt of an Address Byte. The ISL23325 also
responds with an ACK after receiving a Data Byte of a write
operation. The master must respond with an ACK after receiving
a Data Byte of a read operation.
A valid Identification Byte contains 1010 as the four MSBs, and
the following three bits are matching the logic values present at
pins A2, A1 and A0. The LSB is the Read/Write bit. Its value is “1”
for a Read operation and “0” for a Write operation (see Table 3).
TABLE 3. IDENTIFICATION BYTE FORMAT
LOGIC VALUES AT PINS A2, A1 AND A0 RESPECTIVELY
1
0
1
0
A2 A1 A0 R/W
(MSB)
(LSB)
SCL
SDA
START
DATA
DATA
DATA
STABLE CHANGE STABLE
FIGURE 27. VALID DATA CHANGES, START AND STOP CONDITIONS
STOP
15
FN7870.0
June 21, 2011