ISL23315_15 Datasheet, PDF (8/20 Pages) Intersil Corporation – Single, Low Voltage Digitally Controlled Potentiometer(XDCP™)

ISL23315
Serial Interface Specification for SCL, SDA, A0, A1 Unless Otherwise Noted. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 20)
TYP
(Note 8)
MAX
(Note 20)
UNITS
t_HD:STA
t_SU:DAT
t_HD:DAT
t_SU:STO
t_HD:STO
t_DH
t_R
t_F
Cb
START Condition Hold Time
Input Data Set-up Time
Input Data Hold Time
STOP Condition Set-up Time
STOP Condition Hold Time for Read
or Write
Output Data Hold Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Capacitive Loading of SDA or SCL
From SDA falling edge
crossing 30% of V_LOGIC to SCL
falling edge crossing 70% of
V_LOGIC
From SDA exiting the 30% to
70% of V_LOGIC window, to SCL
rising edge crossing 30% of
V_LOGIC
From SCL falling edge crossing
70% of V_CC to SDA entering
the 30% to 70% of V_CC window
From SCL rising edge crossing
70% of V_LOGIC, to SDA rising
edge crossing 30% of V_LOGIC
From SDA rising edge to SCL
falling edge; both crossing
70% of V_CC (Note 11)
From SCL falling edge crossing
30% of V_LOGIC, until SDA
enters the 30% to 70% of
V_LOGIC window.
I_OL = 3mA, V_LOGIC > 2V.
I_OL = 0.5mA, V_LOGIC < 2V
From 30% to 70% of V_LOGIC
From 70% to 30% of V_LOGIC
Total on-chip and off-chip
(Note 11)
600
100
0
600
1300
0
20 + 0.1 x Cb
20 + 0.1 x Cb
10
ns
ns
ns
ns
ns
ns
250
ns
250
ns
400
pF
t_SU:A
A1, A0 Setup Time
Before START condition
600
ns
t_HD:A
A1, A0 Hold Time
After STOP condition
600
ns
NOTES:
8. Typical values are for T_A = +25°C and 3.3V supply voltages.
9. LSB = [V(RW)₂₅₅ – V(RW)₀]/255. V(RW)₂₅₅ and V(RW)₀ are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the incremental
voltage when changing from one tap to an adjacent tap.
10. ZS error = V(RW)₀/LSB.
11. FS error = [V(RW)₂₅₅ – V_CC]/LSB.
12. DNL = [V(RW)_i – V(RW)_i-1]/LSB-1, for i = 1 to 255. i is the DCP register setting.
13. INL = [V(RW)_i – i • LSB – V(RW)₀]/LSB for i = 1 to 255
14.
15.
MI ^T=C|^VRW⁼ ₂^M--₅^---₅^{-a----x–-----}RV^---V-W^{--R---R}₀^--W-|^-W---/^--2^{i-i---}5^-+-–-5^--2-M-.^-5--M^-i-°-n--I^-C--i^-s^{-V---}a^---R--m^--W---i^--n^---i^i-m^{- }um+^----1--1-i^-6n--0-c5^---6r^-°-e^---Cm-- entfvo. ^oRrliWta=₂^g1₅^e6₅^{atanond2dM5Ri5nW(d}₀^{)eicasirmtehatehl,meTmi=nei-m4a0suu°mrCevdtaorlue+es1is2otf5at°nhCcee. wsMifapoxer(rt)hvieoslDttahCgePemroeavgxeiirsmttehuremsteevtmatloupeeFrFoafhtutehrxeearwnaidnpge0er0.}
hex respectively.
16. Roffset = RW₀/MI, when measuring between RW and RL.
Roffset = RW₂₅₅/MI, when measuring between RW and RH.
17. RDNL = (RW_i – RW_i-1)/MI -1, for i = 16 to 255.
18. RINL = [RW_i – (MI • i) – RW₀]/MI, for i = 16 to 255.
19.
TC_R
=
-^--^M-----^a----^x---^--^R-----ⁱ--^---–-----^M-----ⁱ--ⁿ----^--^R----ⁱ--^---^
R i  + 25 °C 

------¹----⁰----⁶-------
+ 165 °C
for i = 16 to 255, T = -40°C to +125°C. Max( ) is the maximum value of the resistance and Min( ) is the
minimum value of the resistance over the temperature range.
20. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
21. It is preferable to ramp up both the V_LOGIC and the V_CC supplies at the same time. If this is not possible it is recommended to ramp-up the V_LOGIC
first followed by the V_CC.
8
FN7778.2
August 12, 2015