ISL23315_15 Datasheet, PDF (7/20 Pages) Intersil Corporation – Single, Low Voltage Digitally Controlled Potentiometer(XDCP™)

ISL23315
Operating Specifications V_CC = 2.7V to 5.5V, V_LOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise
stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 20)
TYP
(Note 8)
MAX
(Note 20)
UNITS
t_DCP Wiper Response Time
W option; SCL rising edge of the
0.4
µs
acknowledge bit after data byte to wiper
new position from 10% to 90% of the
final value.
U option; SCL rising edge of the
1.5
µs
acknowledge bit after data byte to wiper
new position from 10% to 90% of the
final value.
T option; SCL rising edge of the
3.5
µs
acknowledge bit after data byte to wiper
new position from 10% to 90% of the
final value.
I_LkgDig Leakage Current, at Pins A0, A1, SDA, Voltage at pin from GND to V_LOGIC
SCL
tShdnRec DCP Recall Time from Shutdown Mode SCL rising edge of the acknowledge bit
after ACR data byte to wiper recalled
position and RH connection
V_CC, V_LOGIC V_{CC ,}V_LOGIC Ramp Rate
Ramp
(Note 21)
Ramp monotonic at any level
-0.4
0.01
<0.1
1.5
0.4
µA
µs
50
V/ms
Serial Interface Specification for SCL, SDA, A0, A1 Unless Otherwise Noted.
SYMBOL
V_IL
V_IH
Hysteresis
V_OL
C_pin
f_SCL
t_sp
t_AA
t_BUF
t_LOW
t_HIGH
t_SU:STA
PARAMETER
Input LOW Voltage
Input HIGH Voltage
SDA and SCL Input Buffer
Hysteresis
SDA Output Buffer LOW Voltage
SDA, SCL Pin Capacitance
SCL Frequency
Pulse Width Suppression Time at
SDA and SCL Inputs
SCL Falling Edge to SDA Output
Data Valid
Time the Bus Must be Free Before
the Start of a New Transmission
Clock LOW Time
Clock HIGH Time
START Condition Set-up Time
TEST CONDITIONS
V_LOGIC > 2V
V_LOGIC <2V
I_OL = 3mA, V_LOGIC > 2V
I_OL = 1.5mA,
V_LOGIC <2V
MIN
(Note 20)
-0.3
0.7 x V_LOGIC
0.05 x V_LOGIC
0.1 x V_LOGIC
0
Any pulse narrower than the
max spec is suppressed
SCL falling edge crossing 30%
of V_LOGIC, until SDA exits the
30% to 70% of V_LOGIC window
SDA crossing 70% of V_LOGIC
during a STOP condition, to
SDA crossing 70% of V_LOGIC
during the following START
condition
Measured at the 30% of
V_LOGIC crossing
Measured at the 70% of
V_LOGIC crossing
SCL rising edge to SDA falling
edge; both crossing 70% of
V_LOGIC
1300
1300
600
600
TYP
(Note 8)
10
MAX
(Note 20)
0.3 x V_LOGIC
V_LOGIC + 0.3
0.4
0.2 x V_LOGIC
400
50
900
UNITS
V
V
V
V
V
pF
kHz
ns
ns
ns
ns
ns
ns
7
FN7778.2
August 12, 2015