HCTS193MS Datasheet, PDF (8/9 Pages) Intersil Corporation – Radiation Hardened Synchronous 4-Bit Up/Down Counter

AC Timing Diagrams
HCTS193MS
I/FMAX
CPU OR CPD _VS
VS
TW
TPHL
QN
VS
VS
INPUT LEVEL
CPU OR CPD ^VS
TPLH
VS
TPHL
TCU OR TCD
VS
INPUT LEVEL
VS
TPLH
VS
FIGURE 1. CLOCK TO OUTPUT DELAYS AND CLOCK PULSE
WIDTH
FIGURE 2. CLOCK TO TERMINAL COUNT DELAYS
PN
TW
PL
VS
VS
CPU
OR
CPD
TPLH
QN
VS
INPUT LEVEL
TW
VS
INPUT LEVEL
VS
TREC
VS
INPUT
LEVEL
TPHL
VS
MR
CPU OR CPD
QN
VS
VS
TW
TREC
VS
TPHL
VS
INPUT LEVEL
INPUT LEVEL
FIGURE 3. PARALLEL LOAD PULSE WIDTH, PARALLEL
LOAD TO OUTPUT DELAYS, AND PARALLEL
LOAD TO CLOCK RECOVERY TIME
FIGURE 4. MASTER RESET PULSE WIDTH, MASTER RESET
TO OUTPUT DELAY AND MASTER RESET TO
CLOCK RECOVERY TIME
PN
VS
TSU(H)
TH
PL
VS
VS
TH
TSU(L)
VS
INPUT
LEVEL
INPUT
LEVEL
VOH
Q=p
QN
Q=p
VOL
FIGURE 5. SETUP AND HOLD TIMES DATA TO PARALLEL
LOAD (PL)
TTLH
20%
80% 80%
OUTPUT
TTHL
20%
FIGURE 6. OUTPUT TRANSITION TIME
AC Timing Diagrams
AC VOLTAGE LEVELS
PARAMETER
VCC
VIH
VS
VIL
GND
HCTS
4.50
3.00
1.30
0
0
UNITS
V
V
V
V
V
AC Load Circuit
DUT
CL
CL = 50pF
RL = 500Ω
TEST
POINT
RL
Spec Number 518620
599