DG526 Datasheet, PDF (8/16 Pages) Intersil Corporation – Analog CMOS Latchable Multiplexers

DG526, DG527, DG528, DG529
Minimum Input Timing Requirements Over Full Temperature Range
PARAMETER
MEASURED TERMINAL
MIN
UNITS
WRITE Pulse Width, t_WW
WR, See Figure 1
300
ns
A, EN Data Valid After WRITE (Stabilization Time), t_DW A₀, A₁, (A₂), EN, WR; See Figure 1
180
ns
A, EN Data Valid After WRITE (Hold Time), t_WD
A₀, A₁, (A₂), EN, WR; See Figure 1
30
ns
RESET Pulse Width, t_RS
RS, (Note 6), V_S = 5V, See Figure 2
500
ns
NOTES:
1. Signals on V_S, V_D or V_IN exceeding V+ or V- will be clamped by internal diodes. Limit diode forward current to maximum current ratings.
2. Typical values are for design aid only, not guaranteed and not subject to production testing.
3. The algebraic convention whereby the most negative value is a minimum, and most positive value is a maximum, is used in this datasheet.
4.
OFF Isolation
=
20--^V----^S--- , where
VD
V_S =
input
to OFF switch, and
V_D = output
due to
V_S .
5. I_D(ON) is leakage from driver into “ON” switch.
6. Period of Reset (RS) pulse must be at least 50µs during or after power ON.
7. Parameter not tested. Parameter guaranteed by design or characterization.
Test Circuits and Waveforms
3V
WR
0
3V
A₀, A₁, (A₂)
EN
0
1.5V
t_WW
t_DW
2.0V
t_WD
0.8V
FIGURE 1. WR TIMING WAVEFORMS
3V
RS
0
V_O
SWITCH
OUTPUT
0V
1.5V
t_RS
t_OFF(RS)
0.8V_O
FIGURE 2. RS TIMING WAVEFORMS
+2.4V
LOGIC
INPUT
50Ω
+15V
V+
EN _DG528† S₁
±10V
RS
S₂ THRU S₇
A₀
S₈
+10V
A₁
SWITCH
OUTPUT
A₂
D
V_D
GND WR V-
1MΩ
35pF
-15V
+2.4V
LOGIC
INPUT
50Ω
+15V
V+
EN
S_1B
DG529†
±10V
RS
S_2A THRU S_{4A ,}
D_A
S_2B, AND S_3B
S_4B
+10V
A₀
SWITCH
A₁
D_B
OUTPUT
V_DB
GND WR V-
1MΩ
35pF
-15V
FIGURE 3A. t_TRANSITION SWITCHING TIME TEST CIRCUIT
† Similar connections for DG526
FIGURE 3B. t_TRANSITION SWITCHING TIME TEST CIRCUIT
† Similar connections for DG527
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