CD4095BMS Datasheet, PDF (8/10 Pages) Intersil Corporation – CMOS Gated J-K Master-Slave Flip-Flops

CD4095BMS, CD4096BMS
trCL
tfCL
CLOCK*
INPUT
VDD
90%
50%
10% ₀
J OR K
GATE INPUTS
tSLH
Q OR Q
OUTPUT
tSHL
tTLH
tPLH
tTHL
tPHL
50%
0
VDD
90%
50%
10% ₀
trCL
CLOCK
tfCL
tWL
tWH
tWL + tWH = ^I
fCL
VDD
90%
50%
10% ₀
FIGURE 2. PROPAGATION DELAY, TRANSITION, AND SETUP FIGURE 3. CLOCK PULSE RISE AND FALL TIME WAVEFORMS
TIME WAVEFORMS
VDD
3
4
5
CLOCK
13
JS
Q
VSS
12 _CL
9
Q
10
11
KR
2
VSS
FIGURE 4. CD4095BMS CONNECTED IN TOGGLE MODE
D
CLOCK
3
4
5
VSS
VDD
11
10
9
13
JS
Q
VSS
12 _CL
Q
KR
2
VSS
FIGURE 5. CD4096BMS CONNECTED AS A “D” TYPE FLIP-FLOP
CLOCK
INPUT
QA
QB
QC
QD
VDD
3
4
5
9
10
11
J
12 _CL
Q8
CD4095BMS
K
Q
3
4
5
J
12 _CL
Q8
CD4095BMS
9
10
11
K
Q
3
4
5
J
12 _CL
Q8
CD4095BMS
9
10
11
K
Q
3
4
5
J
12 _CL
Q8
CD4095BMS
9
10
6
11
K
Q
STATE 0 1 2 3 4 5 6 7 8 9 0 1
CLOCK
QA
QB
QC
QD
STATE QA QB QC QD
0
0000
1
1000
2
0100
3
1100
4
0010
5
1010
6
0110
7
1110
8
0001
9
1001
FIGURE 6. SYNCHRONOUS BINARY DIVIDE-BY-TEN COUNTER
NOTE:
PINS 2 & 13 RESET &
SET, GO TO VSS ON
ALL UNITS
7-1101