CD4095BMS Datasheet, PDF (1/10 Pages) Intersil Corporation – CMOS Gated J-K Master-Slave Flip-Flops

December 1992
CD4095BMS
CD4096BMS
CMOS Gated J-K
Master-Slave Flip-Flops
Features
• Set-Reset Capability
• High Voltage Types (20V Rating)
• CD4095BMS Non-Inverting J and K Inputs
• CD4096BMS Inverting and Non-Inverting J and K
Inputs
• 16MHz Toggle Rate (Typ.) at VDD - VSS = 10V
• Gated Inputs
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Standardized Symmetrical Output Characteristics
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25^oC
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets all requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Applications
• Registers
• Counters
• Control Circuits
Description
CD4095BMS and CD4096BMS are J-K Master-Slave Flip-
Flops featuring separate AND gating of multiple J and K
inputs. The gated J-K inputs control transfer of information
into the master section during clocked operation. Information
on the J-K inputs is transferred to the Q and Q outputs on
the positive edge of the clock pulse. SET and RESET inputs
(active high) are provided for asynchronous operation.
The CD4095BMS and CD4096BMS are supplied in these 14
lead outline packages:
Braze Seal DIP
Frit Seal DIP
H4Q
H1A
Pinouts
CD4095BMS
TOP VIEW
NC 1
RESET 2
J1 3
J2 4
J3 5
Q6
VSS 7
14 VDD
13 SET
12 CLOCK
11 K1
10 K2
9 K3
8Q
CD4096BMS
TOP VIEW
NC 1
RESET 2
J1 3
J2 4
J3 5
Q6
VSS 7
14 VDD
13 SET
12 CLOCK
11 K1
10 K2
9 K3
8Q
NC = NO CONNECTION
Functional Diagrams
SET
J1 ³
J2
J3
4
5
12
CLOCK
K1
11
10
K2
K3
9
RESET
CD4095BMS
13
J
SQ
8
Q
CL
6
K _RQ
Q
2 VDD = 14
VSS = 7
NC = 1
CD4096BMS
SET
J1 ³
J2
J3
4
5
12
CLOCK
K1
K2
K3
11
10
9
RESET
13
J
SQ
8
Q
CL
6
K _RQ
Q
2 VDD = 14
VSS = 7
NC = 1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1094
File Number 3331