CD4095BMS Datasheet, PDF (7/10 Pages) Intersil Corporation – CMOS Gated J-K Master-Slave Flip-Flops

Logic Diagram
CD4095BMS, CD4096BMS
FOR
CD4095BMS
J3
5
*
FOR
CD4096BMS
J3
5
*
FOR
CD4095BMS
J3
9
*
FOR
CD4096BMS
J3
9
*
SET 13 ^*
J1 3 ^*
J2 4 ^*
K1 11 ^*
K2 10 ^*
RESET 2 ^*
CLOCK 12 ^*
*ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION
NETWORK
CL
1
TG
2
CL
1
2
CL
TG
CL
CL
1
TG
2
CL
1
2
TG
CL
CL
6Q
8Q
CL
CL
VDD
TRANSMISSION GATE
1
IN
OUT
TG
INPUT TO OUTPUT IS:
2
a) A BIDIRECTIONAL LOW
IMPEDANCE WHEN CONTROL INPUT 1
IS “LOW” AND CONTROL INPUT 2 IS “HIGH”
b) AN OPEN CIRCUIT WHEN CONTROL INPUT 1
IS “HIGH” AND CONTROL INPUT 2 IS “LOW”
VSS
FIGURE 1. CD4095BMS AND CD4096BMS LOGIC DIAGRAM
SYNCHRONOUS OPERATION
(S = 0, R = 0)
TRUTH TABLES
ASYNCHRONOUS OPERATION
(J AND K = Don’t Care)
INPUTS BEFORE POSITIVE
CLOCK TRANSITION
OUTPUTS AFTER POSITIVE
CLOCK TRANSITION
INPUTS BEFORE POSITIVE
CLOCK TRANSITION
OUTPUTS AFTER POSITIVE
CLOCK TRANSITION
J*
K*
Q
Q
S
R
Q
Q
0
0
No Change
No Change
0
0
No Change
No Change
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
Toggles
Toggles
1
1
0
0
* For CD4095BMS
J = J1 • J2 • J3
K = K1 • K2 • K3
For CD4096BMS
J = J1 • J2 • J3
K = K1 • K2 • K3
0 = VSS, 1 = VDD
7-1100