CD4027BMS Datasheet, PDF (8/8 Pages) Intersil Corporation – CMOS Dual J-K Master-Slave Flip-Flop

CD4027BMS
Typical Performance Characteristics (Continued)
AMBIENT TEMPERATURE (T_A) = +25^oC
250
200
SUPPLY VOLTAGE (VDD) = 5V
150
100
10V
50
15V
AMBIENT TEMPERATURE (T_A) = +25^oC
trl tf = 5ns
CL = 50pF
30
25
20
15
10
5
0
20 40
60 80 100
LOAD CAPACITANCE (CL) (pF)
FIGURE 7. TYPICAL PROPAGATION DELAY TIME vs LOAD
CAPACITANCE (SET TO Q, OR RESET TO Q)
0
5
10
15
20
SUPPLY VOLTAGE (VDD) (V)
FIGURE 8. TYPICAL MAXIMUM CLOCK FREQUENCY vs
SUPPLY VOLTAGE (TOGGLE MODE)
Chip Dimensions and Pad Layout
Dimensions in parentheses are in millimeters
and are derived from the basic inch dimensions
as indicated. Grid graduations are in mils (10^-3 inch)
METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
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