CD4027BMS Datasheet, PDF (4/8 Pages) Intersil Corporation – CMOS Dual J-K Master-Slave Flip-Flop

Specifications CD4027BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
SYMBOL
CONDITIONS
Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V
Input Voltage Low
VIL VDD = 10V, VOH > 9V, VOL < 1V
Input Voltage High
VIH VDD = 10V, VOH > 9V, VOL < 1V
Propagation Delay
Clock To Q, Q
Propagation Delay
Set To Q, Reset To Q
Propagation Delay
Set To Q, Reset To Q
Transition Time
Maximum Clock Input
Frequency Toggle Mode
Input TR, TF = 5ns
Minimum Data Setup
Time
Minimum Set or Reset
Pulse Width
Minimum Clock Pulse
Width
Clock Input Rise Or Fall
Time (Note 5)
Input Capacitance
TPHL1
TPLH1
TPLH2
TPHL3
TTHL
TTLH
FCL
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
TS
TW
TW
TRCL
TFCL
CIN
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
NOTES
1, 2
1, 2
1, 2
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3, 4
1, 2, 3, 4
1, 2, 3, 4
1, 2
TEMPERATURE MIN
+125^oC
-
-55^oC
-
+25^oC, +125^oC,
-
-55^oC
+25^oC, +125^oC,
7
-55^oC
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
8
+25^oC
12
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
MAX
-2.4
-4.2
3
UNITS
mA
mA
V
-
V
130
ns
90
ns
130
ns
90
ns
170
ns
120
ns
100
ns
80
ns
-
MHz
-
MHz
200
ns
75
ns
50
ns
180
ns
80
ns
50
ns
140
ns
60
ns
40
ns
45
µs
5
µs
2
µs
7.5
pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. If more than one unit is cascaded in a parallel clocked operation, trCL should be made less than or equal to the sum of the fixed propa-
gation delay time at 15pF and the transition time of the output driving stage for the estimated capacitive load.
PARAMETER
Supply Current
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
SYMBOL
CONDITIONS
IDD VDD = 20V, VIN = VDD or GND
NOTES
1, 4
TEMPERATURE MIN
+25^oC
-
MAX
7.5
UNITS
µA
7-783