CD4027BMS Datasheet, PDF (6/8 Pages) Intersil Corporation – CMOS Dual J-K Master-Slave Flip-Flop

CD4027BMS
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
9V ± -0.5V
50kHz
25kHz
Static Burn-In 1 1, 2, 14, 15
3 - 13
16
Note 1
Static Burn-In 2
Note 1
1, 2, 14, 15
8
3 - 7, 9 - 13, 16
Dynamic Burn-
-
In Note 2
4, 7 - 9, 12
5, 6, 10, 11, 16
12, 14, 15
3, 13
Irradiation
Note 3
1, 2, 14, 15
8
3 - 7, 9 - 13, 16
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 4.75K ± 5%, VDD = 18V ± 0.5V
3. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V
Logic Diagram
RESET
*4(12)
J
*6(10)
K
*5(11)
SET
*7(9)
CL
MASTER
p
TG
n
CL
CL
p
TG
n
CL
CL
p
SLAVE
TG
n
CL
CL
p
TG
n
CL
Q
2(14)
Q
1(15)
VDD
*3(13)
CLOCK
CL
CL
* ALL INPUTS ARE
PROTECTED BY
CMOS PROTECTION
NETWORK
VSS
LOGIC DIAGRAM AND TRUTH TABLE FOR CD4027BMS (ONE OF TWO IDENTICAL J-K FLIP-FLOPS)
TRUTH TABLE
PRESENT STATE
NEXT STATE
INPUTS
OUTPUT
OUTPUTS
JKSR
Q
CL* Q Q
1X00
0
10
X000
1
10
0X00
0
01
X100
1
01
XX0 0
X
No Change
XX1 0
X
X
10
XX0 1
X
X
01
XX1 1
X
X
11
Logic 1 = High Level
Logic 0 = Low Level
* = Level change
X = Don’t care
7-785