CD4027BMS Datasheet, PDF (1/8 Pages) Intersil Corporation – CMOS Dual J-K Master-Slave Flip-Flop

CD4027BMS
December 1992
CMOS Dual J-K
Master-Slave Flip-Flop
Features
Pinout
• High Voltage Type (20V Rating)
• Set - Reset Capability
CD4027BMS
TOP VIEW
• Static Flip-Flop Operation - Retains State Indefinitely
with Clock Level Either “High” or “Low”
• Medium Speed Operation - 16MHz (typ.) Clock Toggle
Rate at 10V
• Standardized Symmetrical Output Characteristics
• 100% Tested For Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full
Package-Temperature Range;
- 100nA at 18V and +25^oC
Q2 1
Q2 2
CLOCK 2 3
RESET 2 4
K2 5
J2 6
SET 2 7
VSS 8
16 VDD
15 Q1
14 Q1
13 CLOCK 1
12 RESET 1
11 K1
10 J1
9 SET 1
• Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Applications
• Registers, Counters, Control Circuits
Functional Diagram
SET 1
J1 10
K1 11
CLOCK1 13
RESET1 12
SET2 7
VDD
9 16
F/F1
15 ^Q1
14 Q1
Description
CD4027BMS is a single monolithic chip integrated circuit con-
taining two identical complementary-symmetry J-K master-
slave flip-flops. Each flip-flop has provisions for individual J, K,
Set Reset, and Clock input signals. Buffered Q and Q signals
are provided as outputs. This input-output arrangement pro-
vides for compatible operation with the Intersil CD4013B dual D
type flip-flop.
J2 6
K2 5
CLOCK2 3
RESET 2
F/F2
1 Q2
2 Q2
4
8
VSS
The CD4027BMS is useful in performing control, register, and
toggle functions. Logic levels present at the J and K inputs
along with internal self-steering control the state of each flip-
flop; changes in the flip-flop state are synchronous with the pos-
itive-going transition of the clock pulse. Set and reset functions
are independent of the clock and are initiated when a high level
signal is present at either the Set or Reset input.
The CD4027BMS is supplied in these 16-lead outline pack-
ages:
Braze Seal DIP H4T
Frit Seal DIP
H1E
Ceramic Flatpack H6W
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-780
File Number 3302