CD40174BMS Datasheet, PDF (8/8 Pages) Intersil Corporation – CMOS Hex ‘D’-Type Flip-Flop

CD40174BMS
Typical Performance Curves (Continued)
200
AMBIENT TEMPERATURE (T_A) = +25^oC
175
SUPPLY VOLTAGE (VDD) = 5V
150
125
100
10V
75
15V
50
25
0
0 10 20 30 40 50 60 70 80 90 100
LOAD CAPACITANCE (CL) (pF)
FIGURE 8. TYPICAL PROPAGATION DELAY TIME (CLOCK TO OUTPUT) AS A FUNCTION OF LOAD CAPACITANCE
Waveform
Pad Layout
tr CL
CLOCK
INPUT
DATA
INPUT
tSU(LH)*
OUTPUT
tf CL
tH(HL)*
tH(LH)*
tTLH
tSU(HL)*
tTHL
tPLH
tPHL
VDD
90%
50%
10% ₀
VDD
50%
0
VDD
90%
50%
10% ₀
VDD
CLEAR
0
tREM
50%
*(LH) OR (HL) OPTIONAL
FIGURE 9. DEFINITION OF SETUP, HOLD, PROPAGATION
DELAY, AND REMOVAL TIMES
DIMENSIONS AND PAD LAYOUT FOR CD40174BMSH
The photographs and dimensions of each CMOS chip represent a chip when
it is part of the wafer. When the wafer is separated into individual chips, the an-
gle of cleavage may vary with respect to the chip face for different chips. The
actual dimensions of the isolated chip, therefore, may differ slightly from the
nominal dimensions shown. The user should consider a tolerance of -3 mils to
+16 mils applicable to the nominal dimensions shown.
Dimension in parenthesis are in millimeters and are derived from the basic inch
dimensions as indicated. Grid graduations are in mils (10^-3 inch).
METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
7-1391