CD40174BMS Datasheet, PDF (1/8 Pages) Intersil Corporation – CMOS Hex ‘D’-Type Flip-Flop

CD40174BMS
December 1992
CMOS Hex ‘D’-Type Flip-Flop
Features
Pinout
• High Voltage Type (20V Rating)
• 5V, 10V and 15V Parametric Ratings
• Standardized, Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range, 100nA at 18V and +25^oC
• Noise Margin (Over full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Standard
No. 13A, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
CD40174BMS
TOP VIEW
CLEAR 1
Q1 2
D1 3
D2 4
Q2 5
D3 6
Q3 7
VSS 8
16 VDD
15 Q6
14 D6
13 D5
12 Q5
11 D4
10 Q4
9 CLOCK
Applications
• Shift Registers
• Buffer/Storage Registers
• Pattern Generators
Description
Functional Diagram
D1 ³
F/F1
D2 ⁴
F/F2
CD40174BMS consists of six identical ‘D’-Type flip-flops
having independent DATA inputs. The CLOCK and CLEAR
inputs are common to all six units. Data is transferred to the
Q outputs on the positive going transition of the clock pulse.
All six flip-flops are simultaneously reset by a low level on the
CLEAR input.
The CD40174BMS is supplied in these 16 lead outline pack-
ages:
Braze Seal DIP H4T
D3 ⁶
D4 ¹¹
D5 ¹³
F/F3
F/F4
F/F5
Frit Seal DIP
H1E
Ceramic Flatpack H6W
D5 ¹⁴
CLOCK ⁹
CLEAR ¹
F/F6
VSS = 8
VDD = 16
2 _Q1
5 _Q2
7 _Q3
10 _Q4
12 _Q5
15 _Q6
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1384
File Number 3359