CD40174BMS Datasheet, PDF (4/8 Pages) Intersil Corporation – CMOS Hex ‘D’-Type Flip-Flop

Specifications CD40174BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
SYMBOL
CONDITIONS
Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V
Input Voltage Low
Input Voltage High
Propagation Delay
Clock to Output
Propagation Delay
CLEAR to Output
Transition Time
Maximum Clock Input
Frequency
Minimum Data Setup
Time
Minimum Data Hold Time
Minimum Clock Pulse
Width
Maximum Clock Rise and
Fall Time
Minimum CLEAR
Removal Time
Minimum CLEAR Pulse
Width
Input Capacitance
VIL
VIH
TPHL1
TPLH1
TPHL2
TTHL
TTLH
FCL
TS
TH
TW
TRCL
TFCL
TREM
TW
CIN
VDD = 10V, VOH > 9V,
VOL < 1V
VDD = 10V, VOH > 9V,
VOL < 1V
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
CLEAR
All others
NOTES
1, 2
1, 2
1, 2
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3, 4
1, 2, 3, 4
1, 2, 3, 4
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2
1, 2
TEMPERATURE MIN
+125^oC
-
-55^oC
-
+25^oC, +125^oC,
-
-55^oC
+25^oC, +125^oC, +7
-55^oC
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
6
+25^oC
8
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
15
+25^oC
15
+25^oC
15
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
MAX
-2.4
-4.2
3
UNITS
mA
mA
V
-
V
140
ns
100
ns
100
ns
80
ns
100
ns
80
ns
-
MHz
-
MHz
40
ns
20
ns
10
ns
80
ns
40
ns
30
ns
130
ns
60
ns
40
ns
-
µs
-
µs
-
µs
0
ns
0
ns
0
ns
100
ns
50
ns
40
ns
40
pF
7.5
pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. If more than one unit is cascaded, TRCL should be made less than or equal to the sumof the transition time and the fixed propagation
delay of the output of the driving stage for the estimated capacitive load.
7-1387