X9401_06 Datasheet, PDF(7/19 Page) Intersil Corporation – Quad, 64 Tap, Digitally Controlled Potentiometer

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X9401_06 Datasheet, PDF (7/19 Pages) Intersil Corporation – Quad, 64 Tap, Digitally Controlled Potentiometer

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Figure 7. Increment/Decrement Timing Limits

X9401

SCK

tWRID

VW/RW

Voltage Out

INC/DEC CMD Issued

Table 1. Instruction Set

Instruction Set

Instruction

I3 I2 I1 I0 R1 R0 P1 P0

Operation

Read Wiper Counter Register 1 0 0 1 0 0 P1 P0 Read the contents of the Wiper Counter Register

pointed to by P1 - P0

Write Wiper Counter Register 1 0 1 0 0 0 P1 P0 Write new value to the Wiper Counter Register

pointed to by P1 - P0

Read Data Register

1 0 1 1 R1 R0 P1 P0 Read the contents of the Data Register pointed to by

P1 - P0 and R1 - R0

Write Data Register

1 1 0 0 R1 R0 P1 P0 Write new value to the Data Register pointed to by

P1 - P0 and R1 - R0

XFR Data Register to Wiper 1 1 0 1 R1 R0 P1 P0 Transfer the contents of the Data Register pointed to

Counter Register

by R1 - R0 to the Wiper Counter Register pointed to by

P1 - P0

XFR Wiper Counter Register 1 1 1 0 R1 R0 P1 P0 Transfer the contents of the Wiper Counter Register

to Data Register

pointed to by P1 - P0 to the Register pointed to by

R1 - R0

Global XFR Data Register to 0 0 0 1 R1 R0 0 0 Transfer the contents of the Data Registers pointed to

Wiper Counter Register

by R1 - R0 of all four pots to their respective Wiper

Counter Register

Global XFR Wiper Counter

1 0 0 0 R1 R0 0 0 Transfer the contents of all Wiper Counter Registers

to their respective data Registers pointed to by

R1 - R0 of all four pots

Increment/Decrement Wiper 0 0 1 0 0 0 P1 P0 Enable Increment/decrement of the Wiper Counter

Counter Register

Read Status (WIP bit)

0 1 0 1 0 0 0 1 Read the status of the internal write cycle, by

checking the WIP bit.

FN8190.3

October 12, 2006

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