X9401_06 Datasheet, PDF (4/19 Pages) Intersil Corporation – Quad, 64 Tap, Digitally Controlled Potentiometer

X9401
Data Register Detail
(MSB)
(LSB)
D5
D4
D3
D2
D1
D0
NV
NV
NV
NV
NV
NV
Write in Process
The contents of the Data Registers are saved to non-
volatile memory when the CS pin goes from LOW to
HIGH after a complete write sequence is received by
the device. The progress of this internal write opera-
tion can be monitored by a Write In Process bit (WIP).
The WIP bit is read with a Read Status command.
INSTRUCTIONS
Identification (ID) Byte
The first byte sent to the X9401 from the host, follow-
ing a CS going HIGH to LOW, is called the Identifica-
tion byte. The most significant four bits of the slave
address are a device type identifier, for the X9401 this
is fixed as 0101[B] (refer to Figure 1).
The two least significant bits in the ID byte select one
of four devices on the bus. The physical device
address is defined by the state of the A₀ - A₁ input
pins. The X9401 compares the serial data stream with
the address input state; a successful compare of both
address bits is required for the X9401 to successfully
continue the command sequence. The A₀ - A₁ inputs
can be actively driven by CMOS input signals or tied to
V_CC or V_SS.
The remaining two bits in the slave byte must be set to 0.
Figure 1. Identification Byte Format
Device Type
Identifier
0 1 0 1 0 0 A1 A0
Device Address
Instruction Byte
The next byte sent to the X9401 contains the instruc-
tion and register pointer information. The four most
significant bits are the instruction. The next four bits
point to one of the four pots and, when applicable,
they point to one of four associated registers. The for-
mat is shown below in Figure 2.
Figure 2. Instruction Byte Format
Register
Select
I3 I2 I1 I0 R1 R0 P1 P0
Instructions
Pot Select
The four high order bits of the instruction byte specify
the operation. The next two bits (R₁ and R₀) select
one of the four registers that is to be acted upon when
a register oriented instruction is issued. The last two
bits (P1 and P₀) selects which one of the four potenti-
ometers is to be affected by the instruction.
Four of the ten instructions are two bytes in length and
end with the transmission of the instruction byte.
These instructions are:
– XFR Data Register to Wiper Counter Register—This
transfers the contents of one specified Data Register
to the associated Wiper Counter Register.
– XFR Wiper Counter Register to Data Register—This
transfers the contents of the specified Wiper
Counter Register to the specified associated Data
Register.
– Global XFR Data Register to Wiper Counter Register
—This transfers the contents of all specified Data
Registers to the associated Wiper Counter Regis-
ters.
– Global XFR Wiper Counter Register to Data
Register—This transfers the contents of all Wiper
Counter Registers to the specified associated Data
Registers.
The basic sequence of the two byte instructions is illus-
trated in Figure 3. These two-byte instructions
exchange data between the WCR and one of the data
registers. A transfer from a data register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the wiper
to this action will be delayed by t_WRL. A transfer from
the WCR (current wiper position), to a data register is a
write to nonvolatile memory and takes a minimum of
t_WR to complete. The transfer can occur between one
of the four potentiometers and one of its associated reg-
isters; or it may occur globally, where the transfer
occurs between all potentiometers and one associated
register.
Five instructions require a three-byte sequence to
complete. These instructions transfer data between
the host and the X9401; either between the host and
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FN8190.3
October 12, 2006