X9259_14 Datasheet, PDF (7/21 Pages) Intersil Corporation – Single Supply/Low Power/256-Tap/2-Wire Bus Quad Digitally-Controlled Potentiometers

X9259
Identification Byte
The first byte sent to the X9259 from the host is called the
Identification Byte. The most significant four bits are a Device
Type Identifier, ID[3:0] bits, which must be 0101. Refer to
Table 3.
Only the device which Slave Address matches the incoming
device address sent by the master executes the instruction. The
A3 - A0 inputs can be actively driven by CMOS input signals or
tied to V_CC or V_SS.
INSTRUCTION BYTE (I)
The next byte sent to the X9259 contains the instruction and
register pointer information. The four most significant bits are
used provide the instruction opcode I [3:0]. The RB and RA bits
point to one of the four data registers of each associated XDCP.
The least two significant bits point to one of four Wiper Counter
Registers or DCPs. The format is shown in Table 4.
Data Register Selection
REGISTER
DR#0
DR#1
DR#2
DR#3
#: 0, 1, 2, or 3
RB
RA
0
0
0
1
1
0
1
1
The least significant four bits of the Identification Byte are the
Slave Address bits, AD[3:0]. To access the X9259, these four bits
must match the logic values of pins A3, A2, A1, and A0.
ID3
0
(MSB)
DEVICE TYPE IDENTIFIER
ID2
ID1
1
0
TABLE 3. IDENTIFICATION BYTE FORMAT
SLAVE ADDRESS
ID0
A3
A2
A1
1
Logic value of pins A3, A2, A1, and A0
A0
(LSB)
I3
(MSB)
INSTRUCTION OPCODE
I2
I1
TABLE 4. INSTRUCTION BYTE FORMAT
REGISTER SELECTION
I0
RB
RA
DCP SELECTION
(WCR SELECTION)
P1
P0
(LSB)
TABLE 5. INSTRUCTION SET
INSTRUCTION SET
INSTRUCTION
I3 I2 I1 I0 RB RA P1 P0
OPERATION
Read Wiper Counter
Register
1 0 0 1 0 0 1/0 1/0 Read the contents of the Wiper Counter Register pointed
to by P1 - P0
Write Wiper Counter Register
1 0 1 0 0 0 1/0 1/0 Write new value to the Wiper Counter
Register pointed to by P1 - P0
Read Data Register
1 0 1 1 1/0 1/0 1/0 1/0 Read the contents of the Data Register pointed to by
P1 - P0 and RB - RA
Write Data Register
1 1 0 0 1/0 1/0 1/0 1/0 Write new value to the Data Register
pointed to by P1 - P0 and RB - RA
XFR Data Register to Wiper Counter 1 1 0 1 1/0 1/0 1/0 1/0 Transfer the contents of the Data Register pointed to by
Register
P1 - P0 and RB - RA to its
associated Wiper Counter Register
XFR Wiper Counter Register to Data 1 1 1 0 1/0 1/0 1/0 1/0 Transfer the contents of the Wiper Counter Register
Register
pointed to by P1 - P0 to the Data Register pointed to by
RB - RA
Global XFR Data Registers to Wiper 0 0 0 1 1/0 1/0 0
Counter Registers
0 Transfer the contents of the Data Registers pointed to by
RB - RA of all four pots to their respective Wiper Counter
Registers
Global XFR Wiper Counter Registers 1 0 0 0 1/0 1/0 0
to Data Register
0 Transfer the contents of both Wiper Counter Registers to
their respective data Registers pointed to by RB - RA of
all four DCPs
Increment/Decrement Wiper Counter 0 0 1 0 0 0 1/0 1/0 Enable Increment/decrement of the Control Latch
Register
pointed to by P1 - P0
NOTE: 1/0 = data is one or zero
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FN8169.6
December 12, 2014