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| X9259_14 Datasheet, PDF (3/21 Pages) Intersil Corporation – Single Supply/Low Power/256-Tap/2-Wire Bus Quad Digitally-Controlled Potentiometers | |||
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Pin Configuration
X9259
X9259
24 LD SOIC/TSSOP
TOP VIEW
DNC
A0
RW3
RH3
RL3
NC
VCC
RL0
RH0
RW0
A2
WP
1
24
2
23
3
22
4
21
5
20
6
19
X9259
7
18
8
17
9
16
10
15
11
14
12
13
A3
SCL
RL2
RH2
RW2
NC
VSS
RW1
RH1
RL1
A1
SDA
Pin Descriptions
PIN
PIN
#
NAME
DESCRIPTION
2
A0
Device Address for 2-wire bus. (See Note 4)
3
RW3
Wiper Terminal of DCP3
4
RH3
High Terminal of DCP3
5
RL3
Low Terminal of DCP3
7
VCC
System Supply Voltage
8
RL0
Low Terminal of DCP0
9
RH0
High Terminal of DCP0
10
RW0
Wiper Terminal of DCP0
11
A2
Device Address for 2-wire bus. (See Note 4)
12
WP
Hardware Write Protect â Active Low
13
SDA
Serial Data Input/Output for 2-wire bus.
14
A1
Device Address for 2-wire bus. (See Note 4)
15
RL1
Low Terminal of DCP1
16
RH1
High Terminal of DCP1
17
RW1
Wiper Terminal of DCP1
18
VSS
System Ground
20
RW2
Wiper Terminal of DCP2
21
RH2
High Terminal of DCP2
22
RL2
Low Terminal of DCP2
23
SCL
Serial Clock for 2-wire bus.
24
A3
Device Address for 2-wire bus. (See Note 4)
6, 19
NC
No Connect
1
DNC
Do Not Connect
NOTE:
4. A0 through A3 Device address pins must be tied to a logic level.
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3
FN8169.6
December 12, 2014
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