X9259_14 Datasheet, PDF (6/21 Pages) Intersil Corporation – Single Supply/Low Power/256-Tap/2-Wire Bus Quad Digitally-Controlled Potentiometers

X9259
Serial Interface
The X9259 supports a bidirectional bus oriented protocol. The
protocol defines any device that sends data onto the bus as a
transmitter and the receiving device as the receiver. The device
controlling the transfer is a master and the device being
controlled is the slave. The master always initiates data transfers
and provide the clock for both transmit and receive operations.
Therefore, the X9259 operates as a slave device in all
applications.
All 2-wire interface operations must begin with a START, followed
by an Identification Byte, that selects the X9259. All
communication over the 2-wire interface is conducted by sending
the MSB of each byte of data first.
Clock and Data Conventions
Data states on the SDA line can change only during SCL LOW
periods. SDA state changes during SCL HIGH are reserved for
indicating START and STOP conditions (see Figure 2). On
power-up of the X9259, the SDA pin is in the input mode.
START Condition
All commands to the X9259 are preceded by the start condition,
which is a HIGH to LOW transition of SDA while SCL is HIGH. The
X9259 continuously monitors the SDA and SCL lines for the
START condition and does not respond to any command until this
condition is met (see Figure 2).
STOP Condition
All communications must be terminated by a STOP condition,
which is a LOW to HIGH transition of SDA while SCL is HIGH, (see
Figure 2). The STOP condition is also used to place the device
into the Standby Power mode after a Read sequence. A STOP
condition can only be issued after the transmitting device has
released the bus.
Acknowledge
An ACK, Acknowledge, is a software convention used to indicate
a successful data transfer. The transmitting device, either master
or slave, releases the SDA bus after transmitting eight bits.
During the ninth clock cycle, the receiver pulls the SDA line LOW
to acknowledge the reception of the eight bits of data, (see
Figure 3).
The X9259 responds with an ACK after recognition of a START
condition followed by a valid Identification Byte, and once again
after successful receipt of an Instruction Byte. The X9259 also
responds with an ACK after receiving a Data Byte after a Write
Instruction.
A valid Identification Byte contains the Device Type Identifier
0101, as the four MSBs, and the Device Address bits matching
the logic states of pins A3, A2, A1, and A0, as the four LSBs (see
Figure 4 on page 8).
In the Read mode, the device transmits eight bits of data,
releases the SDA line, and then monitors the line for an ACK. The
device continues transmitting data if an ACK is detected. The
device terminates further data transmissions if an ACK is not
detected. The master must then issue a STOP condition to place
the device into a known state.
During the internal nonvolatile Write operation, the X9259
ignores the inputs at SDA and SCL, and does not issue an ACK
after Identification bytes.
SCL
SDA
START
DATA
DATA
DATA
STABLE CHANGE STABLE
FIGURE 2. VALID DATA CHANGES, START, AND STOP CONDITIONS
STOP
SCL FROM
MASTER
1
8
SDA OUTPUT FROM
TRANSMITTER
SDA OUTPUT FROM
RECEIVER
START
FIGURE 3. ACKNOWLEDGE RESPONSE FROM RECEIVER
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December 12, 2014