X9259 Datasheet, PDF (7/21 Pages) Xicor Inc. – Quad Digitally-Controlled (XDCP) Potentiometers

X9259
SCL
SDA
START
DATA DATA DATA
STABLE CHANGE STABLE
STOP
FIGURE 2. VALID DATA CHANGES, START, AND STOP CONDITIONS
SCL from
Master
1
SDA Output from
Transmitter
8
9
SDA Output from
Receiver
START
ACK
FIGURE 3. ACKNOWLEDGE RESPONSE FROM RECEIVER
Identification Byte
The first byte sent to the X9259 from the host is called the
Identification Byte. The most significant four bits are a
Device Type Identifier, ID[3:0] bits, which must be 0101.
Refer to Table 3.
Only the device which Slave Address matches the incoming
device address sent by the master executes the instruction.
The A3 - A0 inputs can be actively driven by CMOS input
signals or tied to V_CC or V_SS.
INSTRUCTION BYTE (I)
The next byte sent to the X9259 contains the instruction and
register pointer information. The four most significant bits are
used provide the instruction opcode I [3:0]. The RB and RA
bits point to one of the four data registers of each associated
XDCP. The least two significant bits point to one of four
Wiper Counter Registers or DCPs. The format is shown in
Table 4.
Data Register Selection
REGISTER
DR#0
DR#1
DR#2
DR#3
RB
RA
0
0
0
1
1
0
1
1
#: 0, 1, 2, or 3
The least significant four bits of the Identification Byte are
the Slave Address bits, AD[3:0]. To access the X9259, these
four bits must match the logic values of pins A3, A2, A1, and
A0.
7
FN8169.2
September 16, 2005