X9221A Datasheet, PDF (7/15 Pages) Intersil Corporation – 64 Taps, 2-Wire Serial Bus

X9221A
Table 1. Instruction Set
Instruction Format
Instruction
Read WCR
I₃ I₂ I₁ I₀ 0 P₀ R₁ R₀
Operation
1 0 0 1 0 1/0 N/A⁽⁷⁾ N/A Read the contents of the Wiper Counter Register
pointed to by P₀
Write WCR
1010
0 1/0 N/A N/A Write new value to the Wiper Counter Register
pointed to by P₀
Read Data Register
1011
0 1/0 1/0 1/0 Read the contents of the Register pointed to by
P₀ and R₁–R₀
Write Data Register
1100
0 1/0 1/0 1/0 Write new value to the Register pointed to by P₀
and R₁–R₀
XFR Data Register to 1 1 0 1
WCR
0 1/0 1/0 1/0 Transfer the contents of the Register pointed to
by P₀ and R₁–R₀ to its associated WCR
XFR WCR to Data
Register
1110
0 1/0 1/0 1/0 Transfer the contents of the WCR pointed to by
P₀ to the Register pointed to by R₁–R₀
Global XFR Data
Register to WCR
0 0 0 1 N/A N/A 1/0 1/0 Transfer the contents of the Data Registers
pointed to by R₁–R₀ of both pots to their
respective WCR
Global XFR WCR
to Data Register
1 0 0 0 N/A N/A 1/0 1/0 Transfer the contents of all WCRs to their
respective data Registers pointed to by R₁–R₀
of both pots
Increment/Decrement 0 0 1 0
Wiper
0 1/0 N/A N/A Enable Increment/decrement of the WCR point-
ed to by P₀
Note: (7) N/A = Not applicable or don’t care; that is, a data register is not involved in the operation and need not be addressed (typical)
Figure 7. Acknowledge Response from Receiver
SCL from
Master
1
Data Output
from Transmitter
8
9
Data Output
from Receiver
START
Acknowledge
7
FN8163.1
September 14, 2005