X9221A Datasheet, PDF (5/15 Pages) Intersil Corporation – 64 Taps, 2-Wire Serial Bus

X9221A
Instruction Structure
The next byte sent to the X9221A contains the instruc-
tion and register pointer information. The four most
significant bits are the instruction. The next four bits
point to one of two pots and when applicable they
point to one of four associated registers. The format is
shown below in Figure 2.
Figure 2. Instruction Byte Format
t
Potentiometer
Select
I3 I2 I1 I0 0 P0 R1 R0
Instructions
Register
Select
The four high order bits define the instruction. The
sixth bit (P0) selects which one of the two potentiome-
ters is to be affected by the instruction. The last two
bits (R1 and R0) select one of the four registers that is
to be acted upon when a register oriented instruction
is issued.
Four of the nine instructions end with the transmission
of the instruction byte. The basic sequence is illus-
trated in Figure 3. These two-byte instructions
exchange data between the WCR and one of the data
registers. A transfer from a data register to a WCR is
essentially a write to a static RAM. The response of
the wiper to this action will be delayed t_STPWV. A
Figure 3. Two-Byte Command Sequence
transfer from WCR’s current wiper position to a data
register is a write to nonvolatile memory and takes a
minimum of t_WR to complete. The transfer can occur
between either potentiometer and their associated
registers or it may occur between both of the potenti-
ometers and one of their associated registers.
Four instructions require a three-byte sequence to
complete. These instructions transfer data between
the host and the X9221A; either between the host and
one of the data registers or directly between the host
and the WCR. These instructions are: Read WCR,
read the current wiper position of the selected pot;
Write WCR, change current wiper position of the
selected pot; Read Data Register, read the contents of
the selected nonvolatile register; Write Data Register,
write a new value to the selected data register. The
sequence of operations is shown in Figure 4.
The Increment/Decrement command is different from
the other commands. Once the command is issued
and the X9221A has responded with an acknowledge,
the master can clock the selected wiper up and/or
down in one segment steps; thereby, providing a fine
tuning capability to the host. For each SCL clock pulse
(t_HIGH) while SDA is HIGH, the selected wiper will
move one resistor segment towards the V_H/R_H termi-
nal. Similarly, for each SCL clock pulse while SDA is
LOW, the selected wiper will move one resistor seg-
ment towards the V_L/R_L terminal. A detailed illustra-
tion of the sequence and timing for this operation are
shown in Figures 5 and 6 respectively.
SCL
SDA
S 0 1 0 1 A3 A2 A1 A0 _A I3 I2 I1 I0 0 P0 R1 R0 _A S
T
C
CT
A
K
KO
R
P
T
5
FN8163.1
September 14, 2005