X9221A Datasheet, PDF (3/15 Pages) Intersil Corporation – 64 Taps, 2-Wire Serial Bus

X9221A
PIN DESCRIPTIONS
Host Interface Pins
Serial Clock (SCL)
The SCL input is used to clock data into and out of the
X9221A.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs. An open drain output requires
the use of a pull-up resistor. For selecting typical val-
ues, refer to the guidelines for calculating typical val-
ues on the bus pull-up resistors graph.
Address
The Address inputs are used to set the least signifi-
cant 4 bits of the 8-bit slave address. A match in the
slave address serial data stream must be made with
the Address input in order to initiate communication
with the X9221A
Potentiometer Pins
V_H/R_H(V_H0/R_H0-V_H1/R_H1), V_L/R_L (V_L0/R_L0-V_L1/R_L1)
The V_H/R_H and V_L/R_L inputs are equivalent to the ter-
minal connections on either end of a mechanical
potentiometer.
V_W/R_W (V_W0/R_W0-V_W1/R_W1)
The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.
PIN CONFIGURATION
DIP/SOIC
V_W0/R_W0
V_L0/R_L0
V_H0/R_L0
A0
A2
V_W1/R_W1
V_L1/R_L1
V_H1/R_H1
SDA
V_SS
1
20
2
19
3
18
4
17
5
16
X9221A
6
15
7
14
8
13
9
12
10
11
V_CC
RES
RES
RES
A1
A3
SCL
RES
RES
RES
PIN NAMES
Symbol
SCL
SDA
A0–A3
V_H0/R_H0-V_H1/R_H1,
V_L0/R_H0-V_L1/R_L0
V_W0/R_W0-V_W1/R_W1
RES
Description
Serial Clock
Serial Data
Address
Potentiometers
(terminal equivalent)
Potentiometers
(wiper equivalent)
Reserved (Do not connect)
PRINCIPLES OF OPERATION
The X9221A is a highly integrated microcircuit incor-
porating two resistor arrays, their associated registers
and counters and the serial interface logic providing
direct communication between the host and the XDCP
potentiometers.
Serial Interface
The X9221A supports a bidirectional bus oriented pro-
tocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device
as the receiver. The device controlling the transfer is a
master and the device being controlled is the slave.
The master will always initiate data transfers and pro-
vide the clock for both transmit and receive operations.
Therefore, the X9221A will be considered a slave
device in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW periods (t_LOW). SDA state changes during
SCL HIGH are reserved for indicating start and stop
conditions.
Start Condition
All commands to the X9221A are preceded by the
start condition, which is a HIGH to LOW transition of
SDA while SCL is HIGH (t_HIGH). The X9221A continu-
ously monitors the SDA and SCL lines for the start
condition, and will not respond to any command until
this condition is met.
Stop Condition
All communications must be terminated by a stop con-
dition, which is a LOW to HIGH transition of SDA while
SCL is HIGH.
3
FN8163.1
September 14, 2005