ISL54056 Datasheet, PDF (7/12 Pages) Intersil Corporation – Ultra Low ON-Resistance, +1.65V to +4.5V, Single Supply, Quad SPDT (Dual DPDT) Analog Switch

ISL54056
Test Circuits and Waveforms (Continued)
V+
C
SIGNAL
GENERATOR
NO or NC
IN 0V or V+
R_ON = V₁/100mA
V_NX
NO or NC
100mA
V₁
V+
C
0V or V+
IN
ANALYZER
R_L
COM
GND
COM
GND
FIGURE 4. OFF ISOLATION TEST CIRCUIT
FIGURE 5. R_ON TEST CIRCUIT
SIGNAL
GENERATOR
NO or NC
IN₁
0V or V+
V+
C
COM
50Ω
ANALYZER
R_L
COM
NC or NO
GND
N.C.
FIGURE 6. CROSSTALK TEST CIRCUIT
Detailed Description
The ISL54056 is a bidirectional, quad single pole/double
throw (SPDT) analog switch that offers precise switching
capability from a single 1.65V to 4.5V supply with low
on-resistance (0.39Ω) and high speed operation
(t_ON = 30ns, t_OFF = 16ns). The device is especially well
suited for portable battery powered equipment due to its low
operating supply voltage (1.65V), low power consumption
(6.3µW max), low leakage currents (165nA max), and the tiny
µTQFN package. The ultra low on-resistance and Ron
flatness provide very low insertion loss and distortion to
applications that require signal reproduction.
Supply Sequencing and Overvoltage Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to GND (see
7
IMPEDANCE
ANALYZER
NO or NC
V+
C
IN 0V or V+
COM
GND
FIGURE 7. CAPACITANCE TEST CIRCUIT
Figure 8). To prevent forward biasing these diodes, V+ must
be applied before any input signals, and the input signal
voltages must remain between V+ and GND.
If these conditions cannot be guaranteed, then precautions
must be implemented to prohibit the current and voltage at
the logic pin and signal pins from exceeding the maximum
ratings of the switch. The following two methods can be used
to provided additional protection to limit the current in the
event that the voltage at a signal pin or logic pin goes below
ground or above the V+ rail.
Logic inputs can be protected by adding a 1kΩ resistor in
series with the logic input (see Figure 8). The resistor limits
the input current below the threshold that produces
permanent damage, and the sub-microamp input current
produces an insignificant voltage drop during normal
operation.
FN6357.1
October 30, 2006