HA457 Datasheet, PDF (7/14 Pages) Intersil Corporation – 95MHz, Low Power, AV = 2, 8 x 8 Video Crosspoint Switch

VIDEO
INPUTS
INPUT
BUFFERS
HA457
HA457
75Ω
VIDEO
OUT
75Ω
OUTPUT
SELECT
WR
LATCH
A2
A1
A0
8X8
SWITCH
MATRIX
A_V = 2
INPUT
SELECT AND
COMMAND
CODES OR
SERIAL I/O
D3
D2
D1/SER OUT
D0/SER IN
FIGURE 5. TYPICAL CABLE DRIVING APPLICATION
Application Information
HA457 Architecture
The HA457 video crosspoint switch consists of 64 switches
in an 8 x 8 grid (Figure 5). Each input is fully buffered and
presents a constant input capacitance whether the input
connects to one output or all eight outputs. This yields
consistent input termination impedances regardless of the
switch configuration. The 8 matrix outputs are followed by 8
gain of 2, wideband, three-stateable buffers optimized for
driving 1kΩ loads. Double terminated video cables
(R_L = 150Ω) may be driven if degraded differential phase is
acceptable (see “Electrical Specification” Table). The output
disable function is useful for multiplexing two or more
HA457s to create a larger input matrix (e.g., two multiplexed
HA457s yield a 16x8 crosspoint).
The HA457 outputs can be disabled individually or
collectively under software control. When disabled, an output
enters a pseudo high-impedance state (R_OUT = 2kΩ). In
multichip parallel applications, the disable function prevents
inactive outputs from loading lines driven by other devices.
Disabling an unused output also reduces power
consumption.
The HA457 outputs connect easily to two HFA1412 quad,
unity gain buffers when 75Ω loads must be driven with
excellent differential phase (see Figures 7 and 21). The
bandwidth improves to 120MHz, while differential gain and
differential phase improve to 0.03% and 0.09 degrees,
respectively.
Power-On RESET
The HA457 has an internal power-on reset (POR) circuit that
disables all outputs at power-up, and presets the switch
matrix so that all outputs connect to IN0. In parallel mode,
the desired switch state may be programmed before the
outputs are enabled. In serial mode, all outputs are
connected to GND each time they are enabled, so switch
state programming must occur after the output is enabled.
Digital Interface
The desired switch state can be loaded using a 7-bit parallel
interface mode or 32-bit serial interface mode (see Tables 1
through 3). All actions associated with the WR line occur on
its rising edge. The same is true for the LATCH line if
EDGE/LEVEL=1. Otherwise, the Slave Register updates
asynchronously (while LATCH=0, if EDGE/LEVEL=0). WR
is logically ANDed with CE and CE to allow active high or
active low chip enable.
7-Bit Parallel Mode
In the parallel programming mode (SER/PAR = 0), the 7
control bits (A2:0 and D3:0) typically specify an output
channel (A2:0) and the corresponding action to be taken
(D3:0). Command codes are available to enable or disable
all outputs, or individual outputs, as shown in Table 1. Each
output has 4-bit Master and Slave Registers associated with
it, that hold the output’s currently selected input address
(defined by D3:0). The input address - if applicable - is
loaded into the Master Register on the rising edge of WR. If
the HA457 is in level mode, and if LATCH=0 (asynchronous
switching), then the input address flows through the
transparent Slave Register, and the output immediately
switches to the new input. For synchronous switching on the
rising edge of LATCH, strap the HA457 for edge mode,
program all the desired switch connections, and then drive
an inverted pulse on the LATCH input. Note: Operations
defined by commands 1011 - 1111 occur asynchronously on
the WR rising edge, without regard for the state of LATCH or
EDGE/LEVEL.
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