HA457 Datasheet, PDF (3/14 Pages) Intersil Corporation – 95MHz, Low Power, AV = 2, 8 x 8 Video Crosspoint Switch

HA457
Pin Descriptions
PIN
MQFP
PLCC
NAME
FUNCTION
3, 6, 17, 28, 39 1, 9, 12, 23, 34
NC
No connect. Not internally connected.
40
2
D1/ SER OUT Parallel Data Bit input D1 for parallel programming mode. Serial Data Output (MSB of shift
register) for cascading multiple HA457s in serial programming mode. Simply connect
Serial Data Out of one HA457 to Serial Data In of another HA457 to daisy chain multiple
devices.
41
3
D0/SER IN Parallel Data Bit input D0 for parallel programming mode. Serial Data Input (input to shift
register) for serial programming mode.
42, 43, 1
4, 5, 7
A2, A1, A0 Output Channel Address Bits. These inputs select the output being programmed in parallel
programming mode.
44, 2, 4, 7, 9, 11, 6, 8, 10, 13,
13, 15
15, 17, 19, 21
IN0-IN7
Analog Video Input Lines.
5, 8
11, 14
DGND
Digital Ground. Connect both DGND pins to AGND.
10
16
EDGE/LEVEL A user strapped input that defines whether synchronous channel switching is edge or level
controlled. With this pin strapped high, the slave register loads from the master register
(thus changing the switch matrix state) on the rising edge of the LATCH signal. If it is
strapped low (level mode), the slave register is transparent while LATCH is low, passing
data directly from the master register to the switch state decoders. Strapping EDGE/LEVEL
and LATCH low causes the channel switch to execute on the WR rising edge (not
recommended for serial mode operation).
12, 23, 38
18, 29, 44
V+
Positive supply voltage. Connect all V+ pins together and decouple each pin to AGND
(Figure 6).
14
20
SER/PAR A user strapped input that defines whether the serial (SER/PAR=1) or parallel
(SER/PAR=0) digital programming interface is being utilized.
16, 32
22, 38
V-
Negative supply voltage. Connect both V- pins together and decouple each pin to AGND
(Figure 6).
18
24
WR
WRITE Input. In serial mode, data shifts into the shift register (Master Register) LSB from
SER IN on the WR rising edge. In parallel mode, the Master Register loads with D3:0 (iff
D3:0=0000 through 1000), or the appropriate action is taken (iff D3:0=1011 through 1111),
on the WR rising edge (see Table 1).
19
25
LATCH
Synchronous channel switch control input. If EDGE/LEVEL = 1, data is loaded from the
Master Register to the Slave Register on the rising edge of LATCH. If EDGE/LEVEL = 0,
data is loaded from the Master to the Slave Register while LATCH = 0. In parallel mode,
commands 1011 through 1110 execute asynchronously, on the WR rising edge,
regardless of the state of LATCH or EDGE/LEVEL. Parallel mode command 1111
executes a software “Latch” (see Table 1).
20
26
CE
Chip Enable. When CE = 0 and CE = 1, the WR line is enabled.
21
27
CE
Chip Enable. When CE = 0 and CE = 1, the WR line is enabled.
22, 24, 26, 29, 28, 30, 32, 35,
31, 33, 35, 37 37, 39, 41, 43
OUT7-OUT0 Analog Video Outputs.
25, 27, 30
31, 33, 36
AGND
Analog Ground.
34
40
D3
Parallel Data Bit Input D3 when SER/PAR = 0. D3 is unused with serial programming.
36
42
D2
Parallel Data Bit Input D2 when SER/PAR = 0. D2 is unused with serial programming.
3