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HA457 Datasheet, PDF (5/14 Pages) Intersil Corporation – 95MHz, Low Power, AV = 2, 8 x 8 Video Crosspoint Switch
HA457
Electrical Specifications VSUPPLY = ±5V, AGND = DGND = 0V, RL = 400Ω (Note 2), Unless Otherwise Specified. (Continued)
PARAMETER
TEST CONDITIONS
(NOTE 3)
TEST TEMP
LEVEL (oC) MIN
TYP MAX UNITS
Digital Input Low Voltage
A
Full
-
-
0.8
V
Digital Input High Voltage
A
25
2.0
-
-
V
A
Full 2.2
-
-
V
SER OUT Logic Low Voltage
SER OUT Logic High Voltage
SER OUT Leakage Current
Serial Mode, IOL = 1.6mA
Serial Mode, IOH = -0.4mA
Output Disabled, VOUT = 2.5V
A
Full
-
-
0.4
V
A
Full 3.0
-
-
V
A
25
-
0.2
5
µA
A
Full
-
1
10
µA
AC CHARACTERISTICS (Note 4)
-3dB Bandwidth (Note 6)
VOUT = 200mVP-P
B
25
-
95
-
MHz
VOUT = 1VP-P
B
25
-
75
-
MHz
VOUT = 2VP-P
B
25
-
60
-
MHz
VOUT = 2VP-P, RL= 150Ω
B
25
-
50
-
MHz
Slew Rate (Note 6)
VOUT = 4VP-P, RL = 150Ω
B
25
-
275
-
V/µs
All Hostile Crosstalk (Note 6)
10MHz, VIN = 1VP-P, RL = 150Ω
B
25
-
-55
-
dB
10MHz, VIN = 1VP-P, RL = 1kΩ
B
25
-
-58
-
dB
All Hostile Off Isolation (Note 6)
10MHz, VIN = 1VP-P, RL = 150Ω
B
25
-
95
-
dB
10MHz, VIN = 1VP-P, RL = 1kΩ
B
25
-
75
-
dB
Differential Phase
NTSC or PAL, RL = 150Ω
B
25
-
0.5
-
DEG
NTSC or PAL, RL = 1kΩ
B
25
-
0.05
-
DEG
NTSC or PAL, RL ≥ 10kΩ
B
25
-
0.05
-
DEG
Differential Gain
NTSC or PAL, RL = 150Ω
B
25
-
0.05
-
%
NTSC or PAL, RL = 1kΩ
B
25
-
0.05
-
%
NTSC or PAL, RL ≥ 10kΩ
B
25
-
0.02
-
%
TIMING CHARACTERISTICS (See Figure 8 for more information)
Write Pulse Width High (tWH)
Write Pulse Width Low (tWL)
Chip-Enable Setup Time to Write (tCS)
Chip-Enable Hold Time From Write (tCH)
Data and Address Setup Time to Write (tDS)
Parallel Mode
Serial Mode
A
Full 20
-
-
ns
A
Full 20
-
-
ns
A
Full
5
-
-
ns
A
Full
5
-
-
ns
A
Full 20
-
-
ns
A
Full 20
-
-
ns
Data and Address Hold Time From Write (tDH)
A
Full 25
-
-
ns
Latch Pulse Width (tL)
A
Full 40
-
-
ns
Latch Delay From Write (tD)
A
Full 40
-
-
ns
LATCH Edge to Output Disabled (tOFF)
Serial Mode
B
Full
-
30
-
ns
LATCH Edge to Output Enabled (tON)
Serial Mode
B
Full
-
185
-
ns
Output Break-Before-Make Delay
(tON - tOFF)
Serial Mode
B
Full
-
155
-
ns
NOTES:
2. For the lowest crosstalk, and the best composite video performance, use RL ≥ 1kΩ.
3. Test Level: A. Production Tested; B. Typical or Guaranteed Limit Based on Characterization; C. Design Typical for Information Only.
4. See AC Test Circuits (Figure 1 through Figure 4).
5. Excludes D1/SER OUT which is a bidirectional terminal and thus falls under the higher Output Leakage limit.
6. See Typical Performance Curves for more information.
5