X80200 Datasheet, PDF (6/16 Pages) Intersil Corporation – Power Supply Swquencer with Power-up System Mnitoring

X80200, X80201, X80202, X80203, X80204
Bus Interface AC Timing
SYMBOL
f_SCL
t_CYC
t_HIGH
t_LOW
t_SU:STA
t_HD:STA
t_SU:STO
t_SU:DAT
t_HD:DAT
t_R
t_F
t_AA
t_DH
T_I
t_BUF
t_SU:A
t_HD:A
PARAMETER
Clock Frequency
Clock Cycle Time
Clock High Time
Clock Low Time
Start Set-up Time
Start Hold Time
Stop Set-up Time
SDA Data Input Set-up Time
SDA Data Hold Time
SCL and SDA Rise Time: TR = (V_ILMAX - 0.15) to
(V_IHMIN+0.15)
SCL and SDA Fall Time: TF = (V_IHMIN - 0.15) to
(V_ILMAX - 0.15)
SCL Low to SDA Data Output Valid Time
SDA Data Output Hold Time
Noise Suppression Time Constant at SCL and SDA inputs
Bus Free Time (Prior to Any Transmission)
A0, A1, A2 Set-up Time
A0, A1, A2 Hold Time
TEST
CONDITION
(Note 1)
SMBUS
MIN MAX
10
100
10
4.0
50
4.7
4.7
4.0
4.0
250
300
1000
(Note 1)
300
(Note 1)
(Note 1)
(Note 1)
(Note 1)
550 1100
300
50
4.7
0
0
Timing Diagrams
t_BUF
SCL
t_SU:STA
SDA IN
t_F
t_SU:DAT
t_HD:STA
t_HIGH
t_LOW
t_HD:DAT
SDA OUT
t_R
t_SU:STO
t_AA
t_DH
2-WIRE BUS
MIN MAX
400
2.5
0.6
1.3
0.6
0.6
0.6
100
0
300
UNITS
kHz
µs
µs
µs
µs
µs
µs
ns
ns
ns
300
ns
250 1100
ns
0
ns
50
ns
1.3
µs
0
ns
0
ns
t_BUF
t_HD:STO
t_HD:DAT
FIGURE 1. BUS TIMING
SCL
SDA IN
A2, A1, A0
6
START
t_SU:A
CLK 1
SLAVE ADDRESS BYTE
CLK 9
t_HD:A
FIGURE 2. ADDRESS PIN TIMING
FN8154.0