X80200 Datasheet, PDF (11/16 Pages) Intersil Corporation – Power Supply Swquencer with Power-up System Mnitoring

X80200, X80201, X80202, X80203, X80204
SERIAL CLOCK AND DATA
Data states on the SDA line can change only during SCL
LOW. SDA state changes during SCL HIGH are reserved for
indicating start and stop conditions. (See Figure 7.)
SCL
SDA
DATA STABLE DATA DATA STABLE
CHANGE
FIGURE 7. VALID DATA CHANGES ON THE SDA BUS
SERIAL START CONDITION
All commands are preceded by the start condition, which is a
HIGH to LOW transition of SDA when SCL is HIGH. The
device continuously monitors the SDA and SCL lines for the
start condition and will not respond to any command until
this condition has been met. (See Figure 8.)
SERIAL STOP CONDITION
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA when SCL is
HIGH, followed by a HIGH to LOW transition on SCL. After
going LOW, SCL can stay LOW or return to HIGH. (See
Figure 8.)
SCL
SDA
START
STOP
FIGURE 8. VALID START AND STOP CONDITIONS
Slave Address Byte
Following a START condition, the master must output a
Slave Address Byte. This byte consists of three parts:
• The Device Type Identifier which consists of the most
significant four bits of the Slave Address. The Device Type
Identifier MUST be set to 1010 in order to select the
device.
• The next 3 bits (SA3 - SA1) are slave address bits. These
bits are compared to the status of the input pins A2–A0.
• The Least Significant Bit of the Slave Address (SA0) Byte
is the R/W bit. This bit defines the operation to be
performed on the device being addressed (as defined in
the bits SA2 - SA1). When the R/W bit is “1”, then a READ
operation is selected. A “0” selects a WRITE operation.
Word Address
The next 8 bits following the slave byte, BA7–BA0,
determine the portion of the device accessed. If all ‘0’s, then
Status Register (SR) is selected. If all ‘1’s, then the Remote
Shutdown Register (RSR) is selected.
Serial Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting eight
bits. During the ninth clock cycle, the receiver will pull the
SDA line LOW to acknowledge that it received the eight bits
of data. (See Figure 9.)
The device will respond with an acknowledge after
recognition of a start condition and if the correct Device
Identifier and Select bits are contained in the Slave Address
Byte. If a write operation is selected, the device will respond
with an acknowledge after the receipt of each subsequent
eight bit word. The device will acknowledge all incoming data
and address bytes, except for the Slave Address Byte when
the Device Identifier and/or Select bits are incorrect.
SCL FROM
1
MASTER
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
FIGURE 9. ACKNOWLEDGE RESPONSE FROM RECEIVER
Write Operation
For a write operation, the device requires the Slave Address
Byte and a Word Address Byte. This gives the master
access to the registers. After receipt of the Word Address
Byte, the device responds with an acknowledge, and awaits
the next eight bits of data. After receiving the 8 bits of the
Data Byte, the device again responds with an acknowledge.
The master then terminates the transfer by generating a stop
condition. (See Figure 11, See Figure 1 for bus timing.)
In order to perform a write operation to Remote Shutdown
Register, the Write Enable Latch (WEL) bit must first be set.
11
FN8154.0