X80200 Datasheet, PDF (2/16 Pages) Intersil Corporation – Power Supply Swquencer with Power-up System Mnitoring

X80200, X80201, X80202, X80203, X80204
Functional Diagram
VDDH
18
VFB
17
DNC
16
GATE_M
15
GATE_H
14
VDDM 19
VDDL 20
SETV 1
REF 2
UVLO_H
UVLO_M
UVLO_L
OSC
CHARGE
PUMP_M
CHARGE
PUMP_H
13 GATE_L
CHARGE
PUMP_L
12 ENS
+
CORE-UP-FIRST
–
CORE-DOWN-LAST
11 GATEH_EN
10 READY
A0 3
2-WIRE
INTERFACE
STATUS REGISTER
REMOTE SHUTDOWN REGISTER
9 SCL
4
GND
5
6
A1
A2
7
8
NC
SDA
Pin Descriptions
PIN NAME
DESCRIPTION
1
SETV Set Voltage. This pin is used for voltage based power sequencing of supplies VDDM and VDDL.
If unused connect to ground.
2
REF Reference voltage. This pin is used for voltage based sequencing. The voltage on this pin is compared to the voltage on the
VFB pin and provides the threshold for turn on of the GATE_M output. Either a voltage source or external resistor divider can
be used to provide the reference. If time based sequencing is used this pin should be tied to VDDH.
3
A0
Slave address pin assignment. It has an Internal pull down resistor. (>10MΩ typical)
4
GND Voltage Ground.
5
A1
Slave address pin assignment. It has an Internal pull down resistor. (>10MΩ typical)
6
A2
Slave Address pin assignment. It has an Internal pull down resistor. (>10MΩ typical)
7
NC
No internal connections.
8
SDA Serial bus data input/output pin.
9
SCL Serial bus clock input pin.
10 READY READY Output Pin: This open-drain output pin goes LOW while VDDH is below UVLO_H and remains LOW for t_PURST after
VDDH goes above UVLO_H. READY goes HIGH after t_PURST.
11 GATEH_EN GATE_H Enable. When this pin is HIGH and VDDH > UVLO_H the charge pump of the GATE_H pin turns on and the output
drives HIGH. When this pin is LOW, the charge pump is disabled and the GATE_H output is LOW. An external RC time delay
can be connected between the enable signal and this pin to delay the GATE_H turn on.
12
ENS Enable Sequence. This pin is used for time-based power sequencing of supplies VDDM and VDDL. If unused, connect to ground.
13 GATE_L GATE_L Output: This output is connected to the gate of an (external) Power Switch “L”. The GATE_L pin is driven HIGH when
charge pump L is enabled and pulled LOW when the charge pump is disabled.
14 GATE_H GATE_H Output: This output is connected to the gate of a (external) Power Switch “H”. The GATE_H pin driven HIGH when
charge pump H is enabled and pulled LOW when the charge pump is disabled.
15 GATE_M GATE_M Output: This output is connected to the gate of a (external) Power Switch “M”. The GATE_M pin driven HIGH when
charge pump M is enabled and pulled LOW when the charge pump is disabled.
16
DNC Do not connect (must be left floating).
17
VFB Voltage Feedback Pin. This input pin is used with voltage based power sequencing to monitor the level of a previously turned-
on supply. If unused, connect to ground.
18 VDDH Primary supply voltage (typically 5V).
19 VDDM Monitored Supply Voltage “M” input.
20 VDDL Monitored Supply Voltage “L” input.
2
FN8154.0