X80200 Datasheet, PDF (12/16 Pages) Intersil Corporation – Power Supply Swquencer with Power-up System Mnitoring

X80200, X80201, X80202, X80203, X80204
Read Operation
A Read operation is initiated in the same manner as a write
operation with the exception that the R/W bit of the Slave
Address Byte is set to one.
Prior to issuing the Slave Address Byte with the R/W bit set to
one, the master must first perform a “dummy” write operation.
The master issues the start condition and the Slave Address
Byte, receives an acknowledge, then issues the Word Address
Byte. After acknowledging receipt of the Word Address Byte,
the master immediately issues another start condition and the
Slave Address Byte with the R/W bit set to one. This is followed
by an acknowledge from the device and then by the data byte
containing the register contents. The master terminates the
read operation by responding with a no-acknowledge and then
issuing a stop condition. The ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read operation,
the master must either issue a stop condition during the
ninth cycle or hold SDA HIGH during the ninth clock cycle
and then issue a stop condition.
See Figure 12 for the address, acknowledge, and data
transfer sequence. See Figure 1 for bus timing.
Operational Notes
The device powers-up in the following state:
• The device is in the low power standby state.
• The WEL bit is set to ‘0’. It is not possible to write to the
device.
• The WEL bit must be set to allow write operations.
• SDA pin is the input mode.
• The data in the RSR powers up in ‘0’ state.
SLAVE ADDRESS
DEVICE TYPE
IDENTIFIER
INTERNAL
DEVICE
ADDRESS
READ/
WRITE
SA7 SA6 SA5 SA4 SA3 SA2 _{SA1 SA0}
101 0
A2 A1 A0 R/W
BIT SA0
0
1
OPERATION
WRITE
READ
WORD ADDRESS
BA7 BA6 BA5 BA4 BA3 BA2
0
0
0
0
0
0
1
1
1
1
1
1
BA1 BA0
00
11
SR
RSR
DATA BYTE
D7 D6 D5 D4 D3 D2 D1 D0
FIGURE 10. ADDRESS FORMAT
12
FN8154.0