X4003-05 Datasheet, PDF (6/16 Pages) Intersil Corporation – Selectable watchdog timer

X4003, X4005
NEW V_CC APPLIED =
OLD V_CC APPLIED - ERROR
EXECUTE
RESET V_TRIP
SEQUENCE
V_TRIP PROGRAMMING
EXECUTE
RESET V_TRIP
SEQUENCE
SET V_CC = V_CC APPLIED =
DESIRED V_TRIP
EXECUTE
SET V_TRIP
SEQUENCE
APPLY 5V TO V_CC
DECREMENT V_CC
(V_CC = V_CC - 50MV)
NEW V_CC APPLIED =
OLD V_CC APPLIED + ERROR
RESET PIN
NO
GOES ACTIVE?
YES
ERROR  EMAX
MEASURED V_TRIP -
DESIRED V_TRIP
-EMAX < ERROR < EMAX
DONE
ERROR  –EMAX
EMAX = MAXIMUM ALLOWABLE V_TRIP ERROR
FIGURE 5. V_TRIP PROGRAMMING SEQUENCE
Control Register
The control register provides the user a mechanism for
changing the watchdog timer settings. Watchdog timer bits
are nonvolatile and do not change when power is removed.
The control register is accessed with a special preamble in the
slave byte (1011) and is located at address 1FFh. It can only be
modified by performing a control register write operation. Only
one data byte is allowed for each register write operation. Prior
to writing to the control register, the WEL and RWEL bits must
be set using a two step process, with the whole sequence
requiring 3 steps. See "Writing to the Control Register" on
page 7.
The user must issue a stop after sending the control byte to
the register to initiate the nonvolatile cycle that stores WD1
and WD0. The X4003/X4005 will not acknowledge any data
bytes written after the first byte is entered.
The state of the control register can be read at any time by
performing a serial read operation. Only one byte is read by
each register read operation. The X4003/X4005 resets itself
after the first byte is read. The master should supply a stop
condition to be consistent with the bus protocol, but a stop is
not required to end this operation.
7
6
5
4
0 WD1 WD0 0
3
2
1
0
0
RWEL WEL 0
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit must be set to “1” prior to a write to the control
register.
6
FN8113.2
June 30, 2008