ISL76161 Datasheet, PDF (6/12 Pages) Intersil Corporation – 12-Bit, +3.3V, 130MSPS, High Speed D/A Converter

ISL76161
Electrical Specifications
AV_DD = DV_DD = +3.3V, V_REF = Internal 1.2V, IOUTFS = 20mA, T_A = +25°C for All Typical Values; Parameters
with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested. (Continued)
PARAMETER
TEST CONDITIONS
T_A = -40°C TO +105°C
MIN TYP MAX
UNITS
Digital Input Capacitance, C_IN
TIMING CHARACTERISTICS
-
5
-
pF
Data Setup Time, t_SU
Data Hold Time, t_HLD
Propagation Delay Time, t_PD
See Figure 13
See Figure 13
See Figure 13
-
1.5
-
1.5
-
1
-
ns
-
ns
-
Clock
Period
Minimum CLK Pulse Width, t_PW1,
t_PW2
See Figure 13, (Note 11)
POWER SUPPLY CHARACTERISTICS (Note 5)
-
2
-
ns
AV_DD Power Supply
DV_DD Power Supply
Analog Supply Current (I_AVDD)
(Note 9)
(Note 9)
3.3V, IOUTFS = 20mA
3.3V, IOUTFS = 2mA
2.7
3.3
3.6
V
2.7
3.3
3.6
V
-
27.5 28.5
mA
-
10
-
mA
Digital Supply Current (I_DVDD)
Supply Current (I_AVDD) Sleep Mode
Power Dissipation
3.3V (Note 7)
3.3V, IOUTFS = Don’t Care
3.3V, IOUTFS = 20mA (Note 7)
-
3.7
5
mA
-
1.5
-
mA
-
103
111
mW
3.3V, IOUTFS = 20mA
-
110
120
mW
3.3V, IOUTFS = 2mA (Note 7)
-
45
-
mW
Power Supply Rejection
Single Supply (Note 8)
-0.125 - +0.125 %FSR/V
NOTES:
4. Gain Error measured as the error in the ratio between the full scale output current and the current through R_SET (typically 625µA). Ideally, the
ratio should be 32.
5. Power supply current measurements are performed with all digital inputs at either DV_DD or DCOM
6. Spectral measurements made with differential transformer coupled output and no external filtering. For multitone testing, the same pattern was
used at different clock rates, producing different output frequencies but at the same ratio to the clock rate.
7. Measured with the clock at 130MSPS and the output frequency at 5MHz.
8. See “Definition of Specifications” on page 9.
9. Recommended operation is from 3.0V to 3.6V. Operation below 3.0V is possible with some degradation in spectral performance. Reduction in
analog output current may be necessary to maintain spectral performance.
10. See “Typical Performance” plots on page 7.
11. Tested in production with a clock pulse width of 50% duty cycle.
6
FN6720.1
September 9, 2008