ISL76161 Datasheet, PDF (11/12 Pages) Intersil Corporation – 12-Bit, +3.3V, 130MSPS, High Speed D/A Converter

ISL76161
R_EQ = 0.5 x (R_LOAD // R_DIFF)
AT EACH OUTPUT
PIN 21
PIN 22
ISL76161
IOUTB
R_DIFF
IOUTA
V_OUT = (2 x IOUTA x R_EQ)V
1:1
R_LOAD
R_LOAD REPRESENTS THE
LOAD SEEN BY THE TRANSFORMER
FIGURE 11. OUTPUT LOADING FOR DATASHEET
MEASUREMENTS
Propagation Delay
The converter requires two clock rising edges for data to be
represented at the output. Each rising edge of the clock
captures the present data word and outputs the previous
data. The propagation delay is therefore 1/CLK, plus <2ns of
settling. See Figure 13.
R_EQ = R_A // [ 0.5 x (R_LOAD // R_DIFF) ], WHERE R_A=R_B
AT EACH OUTPUT
PIN 21
PIN 22
ISL76161
IOUTB
IOUTA
R_A
R_DIFF
R_B
V_OUT = (2 x IOUTA x R_EQ)V
R_LOAD
R_LOAD REPRESENTS THE
LOAD SEEN BY THE TRANSFORMER
FIGURE 12. ALTERNATIVE OUTPUT LOADING
Timing Diagram
CLK
D11-D0
I_OUT
t_PW1
t_PW2
t_SU
W₀
t_HLD
t_SU
W₁
t_PD
t_HLD
t_SU
W₂
t_PD
OUTPUT = W₀
t_HLD
50%
W₃
OUTPUT = W_-1
OUTPUT = W₁
FIGURE 13. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
11
FN6720.1
September 9, 2008