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ISL76161 Datasheet, PDF (5/12 Pages) Intersil Corporation – 12-Bit, +3.3V, 130MSPS, High Speed D/A Converter
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ISL76161
Electrical Specifications
AVDD = DVDD = +3.3V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = +25°C for All Typical Values; Parameters
with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested. (Continued)
PARAMETER
TEST CONDITIONS
TA = -40°C TO +105°C
MIN TYP MAX
UNITS
AC CHARACTERISTICS (Using Figure 12 with RDIFF = 100Ω, RLOAD = RA = RB = 50Ω, Full Scale Output = -2.0dBm)
Spurious Free Dynamic Range,
SFDR Within a Window
fCLK = 130MSPS, fOUT = 20.2MHz, 20MHz Span (Notes 6, 8)
-
85
-
dBc
Spurious Free Dynamic Range,
SFDR to Nyquist (fCLK/2)
fCLK = 130MSPS, fOUT = 50.5MHz (Notes 6, 8)
fCLK = 130MSPS, fOUT = 40.4MHz (Notes 6, 8)
-
57
-
dBc
-
62
-
dBc
fCLK = 130MSPS, fOUT = 20.2MHz (Notes 6, 9)
-
69
-
dBc
fCLK = 130MSPS, fOUT = 10.1MHz (Notes 6, 8)
-
73
-
dBc
fCLK = 130MSPS, fOUT = 5.05MHz, T = +25°C (Notes 6, 8)
70
77
-
dBc
fCLK = 130MSPS, fOUT = 5.05MHz, T = -40°C to +105°C (Notes 6, 8) 67
-
-
dBc
fCLK = 100MSPS, fOUT = 40.4MHz (Notes 6, 8)
-
60
-
dBc
fCLK = 80MSPS, fOUT = 30.3MHz (Notes 6, 8)
-
63
-
dBc
fCLK = 80MSPS, fOUT = 20.2MHz (Notes 6, 8)
-
69
-
dBc
fCLK = 80MSPS, fOUT = 10.1MHz (Notes 6, 8, 10)
-
70
-
dBc
fCLK = 80MSPS, fOUT = 5.05MHz (Notes 6, 8)
-
76
-
dBc
fCLK = 50MSPS, fOUT = 20.2MHz (Notes 6, 8)
-
68
-
dBc
fCLK = 50MSPS, fOUT = 10.1MHz (Notes 6, 8)
-
73
-
dBc
fCLK = 50MSPS, fOUT = 5.05MHz (Notes 6, 8)
-
77
-
dBc
Spurious Free Dynamic Range,
fCLK = 130MSPS, fOUT = 17.5MHz to 27.9MHz, 1.3MHz Spacing,
-
68
-
dBc
SFDR in a Window with Eight Tones 35MHz Span (Notes 6, 8)
fCLK = 80MSPS, fOUT = 10.8MHz to 17.2MHz, 811kHz Spacing,
-
75
-
dBc
15MHz Span (Notes 6, 8)
fCLK = 50MSPS, fOUT = 6.7MHz to 10.8MHz, 490kHz Spacing,
10MHz Span (Notes 6, 8)
-
77
-
dBc
Spurious Free Dynamic Range,
fCLK = 78MSPS, fOUT = 11MHz, in a 20MHz Window, RBW = 30kHz -
90
-
dBc
SFDR in a Window with EDGE or GSM (Notes 6, 8, 10)
Adjacent Channel Power Ratio,
fCLK = 76.8MSPS, fOUT = 19.2MHz, RBW = 30kHz (Notes 6, 8, 10) -
70
-
dB
ACPR with UMTS
VOLTAGE REFERENCE
Internal Reference Voltage, VFSADJ
Internal Reference Voltage Drift
Pin 18 Voltage with Internal Reference
1.2 1.23
-
±40
1.3
V
-
ppm/°C
Internal Reference Output Current
Sink/Source Capability
Reference is not intended to be externally loaded
-
0
-
µA
Reference Input Impedance
-
1
-
MΩ
Reference Input Multiplying Bandwidth (Note 8)
-
1.0
-
MHz
DIGITAL INPUTS D11-D0, CLK
Input Logic High Voltage with
3.3V Supply, VIH
Input Logic Low Voltage with
3.3V Supply, VIL
Sleep Input Current, IIH
Input Logic Current, IIH, IL
Clock Input Current, IIH, IL
(Note 5)
(Note 5)
0.7 *
-
-
V
DVDD
-
-
0.3 *
V
DVDD
-25
-
+25
µA
-20
-
+20
µA
-10
-
+10
µA
5
FN6720.1
September 9, 2008
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