ISL54200 Datasheet, PDF (6/18 Pages) Intersil Corporation – USB 2.0 High/Full Speed Multiplexer

ISL54200
Electrical Specifications - 2.7V to 3.6V Supply Test Conditions: V_DD = +3.3V, GND = 0V, V_INH = 1.4V, V_INL = 0.5V,
V_ENH = 1.4V, V_ENL = 0.5V, (Note 11), Unless Otherwise Specified. Bold-
face limits apply over the operating temperature range, -40°C to
+85°C. (Continued)
PARAMETER
TEST CONDITIONS
TEMP
MIN
MAX
(°C) (Notes 12, 13) TYP (Notes 12, 13) UNITS
FSx OFF Capacitance, C_FSxOFF f = 1MHz, V_DD = 3.3V, IN = 3.3V, EN = 3.3V, +25
-
9
-
pF
V_FSD1 or V_FSD2 = V_COMx = 0V, (See Figure 5)
COM ON Capacitance,
C_COMX(ON)
f = 1MHz, V_DD = 3.3V, IN = 3.3V, EN = 3.3V, +25
-
12
-
pF
V_HSD1 or V_HSD2 = V_COMx = 0V, (See Figure 5)
COM ON Capacitance,
C_COMX(ON)
f = 1MHz, V_DD = 3.3V, IN = 0V, EN = 3.3V,
+25
-
15
-
pF
V_FSD1 or V_FSD2 = V_COMx = 0V, (See Figure 5)
POWER SUPPLY CHARACTERISTICS
Power Supply Range, V_DD
Full
2.7
-
5.5
V
Positive Supply Current, I_DD V_DD = 3.6V, IN = 0V or 3.6V, EN = 0V or 3.6V +25
-
20
60
nA
Full
-
-
500
nA
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, V_INL, V_ENL V_DD = 2.7V to 3.6V
Full
-
-
0.5
V
Input Voltage High, V_INH, V_ENH V_DD = 2.7V to 3.6V
Full
1.4
-
-
V
Input Current, I_INL, I_ENL
V_DD = 3.6V, IN = 0V, EN = 0V
Full
-
10
-
nA
Input Current, I_INH
V_DD = 3.6V, IN = 3.6
Full
-
10
-
nA
Input Current, I_ENH
V_DD = 3.6V, EN = 3.6
Full
-
1
-
μA
NOTES:
11. V_LOGIC = Input voltage to perform proper function.
12. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data
sheet.
13. Parts are 100% tested at +25°C. Over temperature limits established by characterization and are not production tested.
14. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal
range.
15. r_ON matching between channels is calculated by subtracting the channel with the highest max r_ON value from the channel with
lowest max r_ON value, between HSD2 and HSD1 or between FSD2 and FSD1.
Test Circuits and Waveforms
VINH
LOGIC
INPUT
VINL
SWITCH
INPUT
VINPUT
SWITCH
OUTPUT _0V
50%
tOFF
VOUT
90%
tON
tr < 20ns
tf < 20ns
90%
VDD
VINPUT
SWITCH
INPUT
EN
HSx or FSx
IN
COMx
VIN
GND
VOUT
RL
45Ω
CL
10pF
Logic input waveform is inverted for switches that have the
opposite logic sense.
FIGURE 1A. MEASUREMENT POINTS
Repeat test for all switches. C_L includes fixture and stray
capacitance.
V_OUT
=
V _(INPUT)
---------^R-----^L---------
R_L + r_ON
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
6
FN6408.2
June 17, 2010