ISL267817_14 Datasheet, PDF (6/18 Pages) Intersil Corporation – 12-Bit Differential Input 200kSPS SAR ADC

ISL267817
Timing Specifications Limits established by characterization and are not production tested. +VCC = 5V, f_DCLOCK = 3.2MHz, f_S = 200kSPS,
V_REF = 2.5V; V_CM = V_REF. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
MAX
(Note 6) TYP (Note 6) UNITS
t_dDO DCLOCK Falling Edge to Next DOUT Valid
35
150
ns
t_DIS CS/SHDN Rising Edge to DOUT Disable Time See Note 10
40
50
ns
t_EN DCLOCK Falling Edge to DOUT Enabled
22
100
ns
t_f
DCLOCK Fall Time
1
100
ns
t_r
DCLOCK Rise Time
1
100
ns
NOTE:
10. During characterization, t_DIS is measured from the release point with a 10pF load (see Figure 4) and the equivalent timing using the ADS7817 loading
(3kΩ, 100pF) is calculated.
CS/SHDN
DCLOCK
DOUT
tSUCS
tCYC
POWER
DOWN
tCSD
Hi-Z
tSMPL
NULL
Hi-Z
BIT ^{B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0}
(MSB)
tCONV
Note 11
tDATA
NULL
BIT _{B11 B10 B9 B8}
CS/SHDN
DCLOCK
DOUT
tSUCS
tCYC
POWER
DOWN
tCSD
Hi-Z
tSMPL
NULL
BIT
B11
B10
B9
(MSB)
B8
B7 B6
tCONV
B5
B4
B3
B2
B1
B0
B1
B2
B3
B4
B5 B6
tDATA
B7
B8
Hi-Z
B9 B10 B11
Note 12
NOTES:
11. After completing the data transfer, additional clocks applied while CS/SHDN is low will result in the previous data being retransmitted LSB-first,
followed by indefinite transmission of zeros.
12. After completing the data transfer, additional clocks applied while CS/SHDN is low will result in indefinite transmission of zeros.
FIGURE 3. SERIAL INTERFACE TIMING DIAGRAM
+VCC
R_L
2.85kΩ
OUTPUT
PIN
CL
10pF
FIGURE 4. EQUIVALENT LOAD CIRCUIT
6
FN7877.2
April 19, 2012