ISL267817_14 Datasheet, PDF (5/18 Pages) Intersil Corporation – 12-Bit Differential Input 200kSPS SAR ADC

ISL267817
Electrical Specifications +VCC = +5V, f_DCLOCK = 3.2MHz, f_S = 200kSPS, V_REF = 2.5V; V_CM = V_REF, Typical values are at T_A = +25°C.
Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
MAX
(Note 6) TYP (Note 6)
UNITS
REFERENCE INPUT
VREF VREF Input Range
0.1
2.5
V
VREFLEAK Current Drain
-100 4
100
µA
f_SAMPLE = 12.5kHz
CS/SHDN = +VCC
-20 0.23
20
µA
-3 0.01
3
µA
DIGITAL INPUT/OUTPUT
Logic Family
CMOS
V_IH
Input High Voltage
V_IL
Input Low Voltage
V_OH Output High Voltage
V_OL
Output Low Voltage
Output Coding
I_OH = –250µA
I_OL = 250µA
3
+VCC + 0.3
V
-0.3
0.8
V
3.5
V
0.4
V
Two’s Complement
I_LEAK Input Leakage Current
C_IN
Input Capacitance
I_OZ
Floating-State Output Current
C_OUT Floating-State Output Capacitance
POWER REQUIREMENTS
-1
1
µA
10
pF
-1
1
µA
5
pF
V_CC
Supply Voltage Range
I_CC
Supply Current
Power Down Current
TEMPERATURE RANGE
f_SAMPLE = 12.5kHz (Notes 8, 9)
f_SAMPLE = 12.5kHz (Note 9)
CS/SHDN = +VCC, f_SAMPLE = 0Hz
4.75
5.25
V
430 800
µA
38
µA
223
µA
0.5
3
µA
Specified Performance
-40
+85
°C
NOTES:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
7. The absolute voltage applied to each analog input must be between GND and +VCC to guarantee datasheet performance.
8. f_DCLOCK = 3.2MHz, CS/SHDN = +VCC for 241 clock cycles out of every 256.
9. See “Power vs Throughput Rate” on page 13 for more information regarding lower sample rates.
Timing Specifications Limits established by characterization and are not production tested. +VCC = 5V, f_DCLOCK = 3.2MHz, f_S = 200kSPS,
V_REF = 2.5V; V_CM = V_REF. Boldface limits apply over the operating temperature range, -40°C to +85°C.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
MAX
(Note 6) TYP (Note 6) UNITS
t_SMPL
t_CONV
f_CYC
t_CSD
t_SUCS
t_hDO
Analog Input Sample Time
Conversion Time
Throughput Rate
CS/SHDN Falling Edge to DCLOCK Low
CS/SHDN Falling Edge to DCLOCK Rising Edge
DCLOCK Falling Edge to Current DOUT Not Valid
1.5
2.0 Clk Cycles
12
Clk Cycles
200
kHz
0
ns
30
ns
15
ns
5
FN7877.2
April 19, 2012