ISL267817_14 Datasheet, PDF (13/18 Pages) Intersil Corporation – 12-Bit Differential Input 200kSPS SAR ADC

ISL267817
+5V
0.1µF
+ ^BULK
1 DNC DNC 8
2 VIN
DNC 7
2.5V
3 COMP VOUT 6
4 GND TRIM 5
ISL21090
+VCC
ISL267817
VREF
0.1µF
0.1µF
FIGURE 31. PRECISION VOLTAGE REFERENCE
+5V
VIN 1
VOUT 2
GND
3
ISL21010
+
BULK
0.1µF
1.25, 2.048 OR 2.5V
+VCC
ISL267817
VREF
0.1µF
0.1µF
FIGURE 32. LOWER COST VOLTAGE REFERENCE
POWER-DOWN/STANDBY MODES
The mode of operation of the ISL267817 is selected by
controlling the logic state of the CS/SHDN signal during a
conversion. There are two possible modes of operation: dynamic
mode or static mode. When CS/SHDN is high (deasserted), the
ADC will be in static mode. Conversely, when CS/SHDN is low
(asserted), the device will be in dynamic mode. There are no
minimum or maximum number of DCLOCK cycles required to
enter static mode, which simplifies power management and
allows the user to easily optimize power dissipation versus
throughput for different application requirements.
DYNAMIC MODE
This mode is entered when a conversion result is desired by
asserting CS/SHDN. Figure 33 shows the general diagram of
operation in this mode. The conversion is initiated on the falling
edge of CS/SHDN, as described in the “Serial Digital Interface”
section on page 14. As soon as CS/SHDN is brought high, the
conversion will be terminated and DOUT will go back into
three-state. Sixteen serial clock cycles are required to complete
the conversion and access the complete conversion result.
CS/SHDN may idle high until the next conversion or idle low until
sometime prior to the next conversion. Once a data transfer is
complete, i.e., when DOUT has returned to three-state, another
conversion can be initiated by again bringing CS/SHDN low.
CS/SHDN
DCLOCK
1
10
16
DOUT
NULL BIT AND CONVERSION RESULT
FIGURE 33. NORMAL MODE OPERATION
STATIC MODE
The ISL267817 enters the power-saving static mode
automatically any time CS/SHDN is deasserted. It is not required
that the user force a device into this mode following a conversion
in order to optimize power consumption.
SHORT CYCLING
In cases where a lower resolution conversion is acceptable,
CS/SHDN can be pulled high before 12 DCLOCK falling edges
have elapsed. This is referred to as short cycling, and it can be
used to further optimize power dissipation. In this mode, a lower
resolution result will be acquired, but the ADC will enter static
mode sooner and exhibit a lower average power dissipation than
if the complete conversion cycle were carried out. The acquisition
time (t_ACQ) requirement must be met for the next conversion to
be valid.
POWER-ON RESET
The ISL267817 performs a power-on reset when the supplies are
first activated, which requires approximately 2.5ms to execute.
After this is complete, a single dummy cycle must be executed in
order to initialize the switched capacitor track and hold. A
dummy cycle will take 5μs with an 3.2MHz DCLOCK. Once the
dummy cycle is complete, the ADC mode will be determined by
the state of CS/SHDN. At this point, switching between dynamic
and static modes is controlled by CS/SHDN with no delay
required between states.
POWER vs THROUGHPUT RATE
The ISL267817 provides reduced power consumption at lower
conversion rates by automatically switching into a low-power
mode after completing a conversion. Maximum power savings
are achieved by running SCLK at the maximum rate, as shown in
Figure 34. If SCLK is operated at a fixed 16x multiple of the
13
FN7877.2
April 19, 2012