ISL12028 Datasheet, PDF (6/28 Pages) Intersil Corporation – Real Time Clock/Calendar with EEPROM

ISL12028
Serial Interface (I²C) Specifications (Continued)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
t_IN
Pulse width Suppression Time at Any pulse narrower than the max
SDA and SCL Inputs
spec is suppressed.
50
ns
t_AA
t_BUF
SCL Falling Edge to SDA Output
Data Valid
Time the bus must be free before
the start of a new transmission
SCL falling edge crossing 30% of
V_DD, until SDA exits the 30% to 70%
of V_DD window.
SDA crossing 70% of V_DD during a
STOP condition, to SDA crossing
70% of V_DD during the following
START condition.
1300
900
ns
ns
t_LOW Clock LOW Time
Measured at the 30% of V_DD
1300
ns
crossing.
t_HIGH Clock HIGH Time
Measured at the 70% of V_DD
600
ns
crossing.
t_SU:STA START Condition Setup Time
t_HD:STA START Condition Hold Time
t_SU:DAT Input Data Setup Time
t_HD:DAT Input Data Hold Time
t_SU:STO STOP Condition Setup Time
t_HD:STO
t_DH
STOP Condition Hold Time for
Read, or Volatile Only Write
Output Data Hold Time
t_R
SDA and SCL Rise Time
SCL rising edge to SDA falling edge.
Both crossing 70% of V_DD.
From SDA falling edge crossing 30%
of V_DD to SCL falling edge crossing
70% of V_DD.
From SDA exiting the 30% to 70% of
V_DD window, to SCL rising edge
crossing 30% of V_DD
From SCL falling edge crossing 70%
of V_DD to SDA entering the 30% to
70% of V_DD window.
From SCL rising edge crossing 70%
of V_DD, to SDA rising edge crossing
30% of V_DD.
From SDA rising edge to SCL falling
edge. Both crossing 70% of V_DD.
From SCL falling edge crossing 30%
of V_DD, until SDA enters the 30% to
70% of V_DD window.
From 30% to 70% of V_DD
600
600
100
0
600
600
0
20 +
0.1 x Cb
ns
ns
ns
ns
ns
ns
ns
250
ns
t_F
SDA and SCL Fall Time
From 70% to 30% of V_DD
20 +
0.1 x Cb
250
ns
Cb
Capacitive Loading of SDA or SCL Total on-chip and off-chip
10
400
pF
Cpin SDA, and SCL Pin Capacitance
10
pF
t_WC Non-volatile Write Cycle Time
12
20
ms
10
NOTES:
3. IRQ/F_OUT Inactive (no frequency output and no alarms).
4. V_IL = V_DD x 0.1, V_IH = V_DD x 0.9, f_SCL = 400kHz.
5. V_RESET = 2.63V (V_DD must be greater than V_RESET), V_BAT = 0V.
6. Bit BSW = 0 (Standard Mode), V_BAT ≥ 1.8V.
7. Specified at +25°C.
8. In order to ensure proper timekeeping, the V_{DD SR-} specification must be followed.
9. Parameter is not 100% tested.
10. t_WC is the minimum cycle time to be allowed for any non-volatile Write by the user, it is the time from valid STOP condition at the end of Write
sequence of a serial interface Write operation, to the end of the self-timed internal non-volatile write cycle.
6
FN8233.5
October 18, 2006