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ISL12028 Datasheet, PDF (24/28 Pages) Intersil Corporation – Real Time Clock/Calendar with EEPROM
ISL12028
TABLE 10. I2C, LV RESET, AND BATTERY BACKUP OPERATION SUMMARY (SHADED ROW IS SAME AS X1228 OPERATION)
MODE
SBIB
BIT
BSW
BIT
VBAT
SWITCHOVER
VOLTAGE
I2C ACTIVE IN
BATTERY
BACKUP?
EE PROM WRITE/
READ IN BATTERY
BACKUP?
FREQ/IRQ
ACTIVE?
NOTES
A
0
B
0
(X1228
mode)
C
1
D
1
0 Standard Mode,
NO
VTRIP = 2.2V typ
1
Legacy Mode, YES, only if
VDD < VBAT
VBAT>VRESET
0 Standard Mode,
NO
VTRIP = 2.2V typ
1
Legacy Mode,
NO
VDD < VBAT
NO
YES
NO
NO
YES
YES
YES
YES
Operation of I2C bus down to VDD =
VRESET, then below that no
communications. Battery switchover
at VTRIP.
Operation of I2C bus into battery
backup mode, but only for
VBAT>VDD>VRESET.
Bus must have pull-ups to VBAT.
Operation of I2C bus down to VDD =
VRESET, then below that no
communications. Battery switchover
at VTRIP.
Operation of I2C busdown to VRESET
or VBAT, whichever is higher.
Backup Battery Operation
Many types of batteries can be used with the Intersil RTC
products. 3.0V or 3.6V Lithium batteries are appropriate, and
sizes are available that can power a Intersil RTC device for up
to 10 years. Another option is to use a super capacitor for
applications where VDD may disappear intermittently for short
periods of time. Depending on the value of super capacitor
used, backup time can last from a few days to two weeks (with
>1F). A simple silicon or Schottky barrier diode can be used in
series with VDD to charge the super capacitor, which is
connected to the VBAT pin. Try to use Schottky diodes with
very low leakages, <1µA desirable. Do not use the diode to
charge a battery (especially lithium batteries!).
There are two possible modes for battery backup operation,
Standard and Legacy mode. In Standard mode, there are no
operational concerns when switching over to battery backup
since all other devices functions are disabled. Battery drain
is minimal in Standard mode, and return to Normal VDD
powered operations predictable. In Legacy modes the VBAT
pin can power the chip if the voltage is above VDD and
VTRIP. This makes it possible to generate alarms and
communicate with the device under battery backup, but the
supply current drain is much higher than the Standard mode
and backup time is reduced. In this case if alarms are used
in backup mode, the IRQ/FOUT pull up resistor must be
connected to VBAT voltage source. During initial power up
the default mode is the Standard mode.
2.7-5.5V
VCC
Vback
VSS
Supercapacitor
I2C Communications During Battery backup and
LVR Operation
Operation in Battery Backup mode and LVR is affected by
the BSW and SBIB bits as described earlier. These bits allow
flexible operation of the serial bus and EEPROM in battery
backup mode, but certain operational details need to be
clear before utilizing the different modes. The most
significant detail is that once VDD goes below VRESET, then
I2C communications cease regardless of whether the device
is programmed for I2C operation in battery backup mode.
Table 10 describes 4 different modes possible with using the
BSW and SBIB bits, and how they are affect LVR and battery
backup operation.
• Mode A - In this mode selection bits indicate a low VDD
switchover combined with I2C operation in battery backup
mode. In actuality the VDD will go below VRESET before
switching to battery backup, which will disable I2C
ANYTIME the device goes into battery backup mode.
Regardless of the battery voltage, the I2C will work down
to the VRESET voltage. See Figure 29.
• Mode B - In this mode the selection bits indicate
switchover to battery backup at VDD<VBAT, and I2C
communications in battery backup. In order to
communicate in battery backup mode, the VRESET voltage
must be less than the VBAT voltage AND VDD must be
greater than VRESET. Also, pull-ups on the I2C bus pins
must go to VBAT to communicate. This mode is the same
as the normal operating mode of the X1228 device
• Mode C - In this mode the selection bits indicate a low
VDD switchover combined with no communications in
battery backup. Operation is actually identical to Mode A
with I2C communications down to VDD =VRESET, then no
communications. See Figure 29.
FIGURE 28. SUPERCAPACITOR CHARGING CIRCUIT
24
FN8233.5
October 18, 2006