ISL12020 Datasheet, PDF (6/25 Pages) Intersil Corporation – Low Power RTC with VDD Battery Backed SRAM and Embedded Temp Compensation ±5ppm with Auto Day Light Saving

ISL12020
SDA vs SCL Timing
t_F
t_HIGH
t_LOW
t_R
SCL
t_SU:STA
SDA
(INPUT TIMING)
SDA
(OUTPUT TIMING)
t_SU:DAT
t_HD:STA
t_HD:DAT
t_AA
t_DH
Symbol Table
WAVEFORM INPUTS
Must be steady
OUTPUTS
Will be steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes Allowed
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not Known
N/A
Center Line is
High Impedance
t_SU:STO
t_BUF
6
FN6450.0
March 29, 2007