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ISL12020 Datasheet, PDF (4/25 Pages) Intersil Corporation – Low Power RTC with VDD Battery Backed SRAM and Embedded Temp Compensation ±5ppm with Auto Day Light Saving
ISL12020
I2C Interface Specifications Test Conditions: VDD=+2.7 to +5.5V, Temperature = -20°C to +70°C, unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
TYP
MIN
(Note 7) MAX UNITS NOTES
VIL
SDA and SCL input buffer LOW
voltage
-0.3
0.3 x VDD V
VIH
SDA and SCL Input Buffer HIGH
Voltage
0.7 x VDD
VDD + 0.3 V
Hysteresis
SDA and SCL Input Buffer
Hysteresis
0.05 x VDD
V
VOL
SDA Output Buffer LOW Voltage, VDD = 5V, IOL = 3mA
Sinking 3mA
0.4
V
CPIN
fSCL
tIN
SDA and SCL Pin Capacitance
SCL Frequency
TA = +25°C, f = 1MHz,
VDD = 5V, VIN = 0V,
VOUT = 0V
Pulse Width Suppression Time at Any pulse narrower than the
SDA and SCL Inputs
max spec is suppressed.
10
pF
400
kHz
50
ns
tAA
SCL Falling Edge To SDA Output SCL falling edge crossing
Data Valid
30% of VDD, until SDA exits
the 30% to 70% of VDD
window.
900
ns
tBUF
Time the Bus Must be Free Before SDA crossing 70% of VDD
1300
ns
The Start of a New Transmission during a STOP condition, to
SDA crossing 70% of VDD
during the following START
condition.
tLOW
Clock LOW Time
Measured at the 30% of VDD
1300
ns
crossing.
tHIGH
Clock HIGH Time
Measured at the 70% of VDD
600
ns
crossing.
tSU:STA
START Condition Setup Time
SCL rising edge to SDA
600
falling edge. Both crossing
70% of VDD.
tHD:STA
START Condition Hold Time
From SDA falling edge
600
crossing 30% of VDD to SCL
falling edge crossing 70% of
VDD.
tSU:DAT
Input Data Setup Time
From SDA exiting the 30% to
100
70% of VDD window, to SCL
rising edge crossing 30% of
VDD.
tHD:DAT
Input Data Hold Time
From SCL falling edge
0
crossing 30% of VDD to SDA
entering the 30% to 70% of
VDD window.
tSU:STO
STOP Condition Setup Time
From SCL rising edge
600
crossing 70% of VDD, to SDA
rising edge crossing 30% of
VDD.
tHD:STO
STOP Condition Hold Time
From SDA rising edge to
600
SCL falling edge. Both
crossing 70% of VDD.
ns
ns
ns
900
ns
ns
ns
4
FN6450.0
March 29, 2007