ICL7129 Datasheet, PDF (6/11 Pages) Intersil Corporation – 41/2 Digit LCD, Single-Chip A/D Converter

ICL7129
COMMON, DGND, and “Low Battery”
The COMMON and DGND (Digital GrouND) outputs of the
ICL7129 are generated from internal zener diodes
(Figure 3). COMMON is included primarily to set the com-
mon-mode voltage for battery operation or for any system
where the input signals float with respect to the power sup-
plies. It also functions as a pre-regulator for an external pre-
cision reference voltage source. The voltage between DGND
and V+ is the supply voltage for the logic section of the
ICL7129 including the display multiplexer and drivers. Both
COMMON and DGND are capable of sinking current from
external loads, but caution should be taken to ensure that
these outputs are not overloaded. Figure 4 shows the con-
nection of external logic circuitry to the ICL7129. This con-
nection will work providing that the supply current
requirements of the logic do not exceed the current sink
capability of the DGND pin. If more supply current is
required, the buffer in Figure 5 can be used to keep the load-
ing on DGND to a minimum. COMMON can source approxi-
mately 12mA while DGND has no source capability.
-
+
N
24
V+
3.2V
“LOW
BATTERY”
LOGIC
SECTION
28
5V
COMMON
36
P
DGND
N
23
V-
FIGURE 3. BIASING STRUCTURE FOR COMMON AND DGND
V+
EXTERNAL
LOGIC
EXTERNAL
LOGIC
CURRENT
24
ICL7129
-
+
36
DGND
23
V-
FIGURE 5. BUFFERED DGND
The “LOW BATTERY” annunciator of the display is turned on
when the voltage between V+ and V- drops below 7.2V typi-
cally. The exact point at which this occurs is determined by
the 6.3V zener diode and the threshold voltage of the
N-Channel transistor connected to the V- rail in Figure 3. As
the supply voltage decreases, the N-Channel transistor
connected to the V-rail eventually turns off and the “LOW
BATTERY” input to the logic section is pulled HIGH, turning
on the “LOW BATTERY” annunciator.
I/O Ports
Four pins of the ICL7129 can be used as either inputs or out-
puts. The specific pin numbers and functions are described
in the Pin Description table. If the output function of the pin is
not desired in an application it can easily be overridden by
connecting the pin to V+ (HI) or DGND (LO). This connection
will not damage the device because the output impedance of
these pins is quite high. A simplified schematic of these
input/output pins is shown in Figure 6. Since there is approx-
imately 500kΩ in series with the output driver, the pin (when
used as an output) can only drive very light loads such as
4000 series, 74CXX type CMOS logic, or other high input
impedance devices. The output drive capability of these four
pins is limited to 3µA, nominally, and the input switching
threshold is typically DGND + 2V.
V+
EXTERNAL
LOGIC
24
ICL7129
36
DGND
I_LOGIC
23
V-
FIGURE 4. DGND SINK CURRENT
DP4/OR PIN 20
DP3/UR PIN 21
LATCH/HOLD PIN 22
CONTINUITY PIN 27
≈ 500kΩ
ICL7129
FIGURE 6. “WEAK OUTPUT”
LATCH/HOLD, Overrange, and Underrange Timing
The LATCH/HOLD output (pin 22) will be pulled low during
the last 100 clock cycles of each full conversion cycle. Dur-
ing this time the final data from the ICL7129 counter is
latched and transferred to the display decoder and multi-
plexer. The conversion cycle and LATCH/HOLD timing are
directly related to the clock frequency. A full conversion cycle
takes 30,000 clock cycles which is equivalent to 60,000
oscillator cycles. OverRange (OR pin 20) and UnderRange
3-36